Commit c51f0d3b authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge back earlier cpufreq material for 6.18

parents 4ea5af08 9a1aa642

Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt

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Generic cpufreq driver



It is a generic DT based cpufreq driver for frequency management.  It supports

both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share

clock and voltage across all CPUs.



Both required and optional properties listed below must be defined

under node /cpus/cpu@0.



Required properties:

- None



Optional properties:

- operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for

  details. OPPs *must* be supplied either via DT, i.e. this property, or

  populated at runtime.

- clock-latency: Specify the possible maximum transition latency for clock,

  in unit of nanoseconds.

- voltage-tolerance: Specify the CPU voltage tolerance in percentage.

- #cooling-cells:

     Please refer to

     Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.



Examples:



cpus {

	#address-cells = <1>;

	#size-cells = <0>;



	cpu@0 {

		compatible = "arm,cortex-a9";

		reg = <0>;

		next-level-cache = <&L2>;

		operating-points = <

			/* kHz    uV */

			792000  1100000

			396000  950000

			198000  850000

		>;

		clock-latency = <61036>; /* two CLK32 periods */

		#cooling-cells = <2>;

	};



	cpu@1 {

		compatible = "arm,cortex-a9";

		reg = <1>;

		next-level-cache = <&L2>;

	};



	cpu@2 {

		compatible = "arm,cortex-a9";

		reg = <2>;

		next-level-cache = <&L2>;

	};



	cpu@3 {

		compatible = "arm,cortex-a9";

		reg = <3>;

		next-level-cache = <&L2>;

	};

};

Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml

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@@ -22,6 +22,7 @@ properties: 
        items:

          - enum:

              - qcom,qcm2290-cpufreq-hw

              - qcom,qcs615-cpufreq-hw

              - qcom,sc7180-cpufreq-hw

              - qcom,sc8180x-cpufreq-hw

              - qcom,sdm670-cpufreq-hw
@@ -132,6 +133,7 @@ allOf: 
        compatible:

          contains:

            enum:

              - qcom,qcs615-cpufreq-hw

              - qcom,qdu1000-cpufreq-epss

              - qcom,sa8255p-cpufreq-epss

              - qcom,sa8775p-cpufreq-epss

Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/cpufreq/mediatek,mt8196-cpufreq-hw.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Hybrid CPUFreq for MT8196/MT6991 series SoCs



maintainers:

  - Nicolas Frattaroli <nicolas.frattaroli@collabora.com>



description:

  MT8196 uses CPUFreq management hardware that supports dynamic voltage

  frequency scaling (dvfs), and can support several performance domains.



properties:

  compatible:

    const: mediatek,mt8196-cpufreq-hw



  reg:

    items:

      - description: FDVFS control register region

      - description: OPP tables and control for performance domain 0

      - description: OPP tables and control for performance domain 1

      - description: OPP tables and control for performance domain 2



  "#performance-domain-cells":

    const: 1



required:

  - compatible

  - reg

  - "#performance-domain-cells"



additionalProperties: false



examples:

  - |

    cpus {

            #address-cells = <1>;

            #size-cells = <0>;



            cpu0: cpu@0 {

                device_type = "cpu";

                compatible = "arm,cortex-a720";

                enable-method = "psci";

                performance-domains = <&performance 0>;

                reg = <0x000>;

            };



            /* ... */



            cpu6: cpu@600 {

                device_type = "cpu";

                compatible = "arm,cortex-x4";

                enable-method = "psci";

                performance-domains = <&performance 1>;

                reg = <0x600>;

            };



            cpu7: cpu@700 {

                device_type = "cpu";

                compatible = "arm,cortex-x925";

                enable-method = "psci";

                performance-domains = <&performance 2>;

                reg = <0x700>;

            };

    };



    /* ... */



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        performance: performance-controller@c2c2034 {

            compatible = "mediatek,mt8196-cpufreq-hw";

            reg = <0 0xc220400 0 0x20>, <0 0xc2c0f20 0 0x120>,

                  <0 0xc2c1040 0 0x120>, <0 0xc2c1160 0 0x120>;

            #performance-domain-cells = <1>;

        };

    };

MAINTAINERS

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@@ -6349,6 +6349,12 @@ F: kernel/sched/cpufreq*.c 
F:	rust/kernel/cpufreq.rs

F:	tools/testing/selftests/cpufreq/









CPU FREQUENCY DRIVERS - VIRTUAL MACHINE CPUFREQ









M:	Saravana Kannan <saravanak@google.com>









L:	linux-pm@vger.kernel.org









S:	Maintained









F:	drivers/cpufreq/virtual-cpufreq.c

















CPU HOTPLUG









M:	Thomas Gleixner <tglx@linutronix.de>









M:	Peter Zijlstra <peterz@infradead.org>
































arch/arm64/boot/dts/ti/k3-am62p5.dtsi



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−1






























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@@ -135,7 +135,7 @@ opp-800000000 {

















		opp-1000000000 {









			opp-hz = /bits/ 64 <1000000000>;









			opp-supported-hw = <0x01 0x0006>;









			opp-supported-hw = <0x01 0x0007>;









			clock-latency-ns = <6000000>;









		};