Unverified Commit c55af006 authored by Nitin Gote's avatar Nitin Gote Committed by Rodrigo Vivi
Browse files

drm/i915/display: fix typos in i915/display files 



Fix all typos in files under drm/i915/display reported by codespell tool.

v2:
  - Include british and american spelling, as those are
    not typos.
  - Fix commenting style. <Jani>

v3: Fix "In case" wrongly capitalized and
    also fix comment style. <Krzysztof Niemiec>

Signed-off-by: default avatarNitin Gote <nitin.r.gote@intel.com>
Reviewed-by: default avatarKrzysztof Niemiec <krzysztof.niemiec@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250120081517.3237326-8-nitin.r.gote@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 5b056be1

drivers/gpu/drm/i915/display/dvo_ns2501.c

+1 −1
Original line number Diff line number Diff line
@@ -517,7 +517,7 @@ static enum drm_connector_status ns2501_detect(struct intel_dvo_device *dvo) 
	 * Even if not, the detection bit of the 2501 is unreliable as

	 * it only works for some display types.

	 * It is even more unreliable as the PLL must be active for

	 * allowing reading from the chiop.

	 * allowing reading from the chip.

	 */

	return connector_status_connected;

}

drivers/gpu/drm/i915/display/i9xx_wm.c

+3 −3
Original line number Diff line number Diff line
@@ -446,7 +446,7 @@ static const struct intel_watermark_params i845_wm_info = { 
 * @latency: Memory wakeup latency in 0.1us units

 *

 * Compute the watermark using the method 1 or "small buffer"

 * formula. The caller may additonally add extra cachelines

 * formula. The caller may additionally add extra cachelines

 * to account for TLB misses and clock crossings.

 *

 * This method is concerned with the short term drain rate
@@ -493,7 +493,7 @@ static unsigned int intel_wm_method1(unsigned int pixel_rate, 
 * @latency: Memory wakeup latency in 0.1us units

 *

 * Compute the watermark using the method 2 or "large buffer"

 * formula. The caller may additonally add extra cachelines

 * formula. The caller may additionally add extra cachelines

 * to account for TLB misses and clock crossings.

 *

 * This method is concerned with the long term drain rate
@@ -1562,7 +1562,7 @@ static int vlv_compute_fifo(struct intel_crtc_state *crtc_state) 
	/*

	 * When enabling sprite0 after sprite1 has already been enabled

	 * we tend to get an underrun unless sprite0 already has some

	 * FIFO space allcoated. Hence we always allocate at least one

	 * FIFO space allocated. Hence we always allocate at least one

	 * cacheline for sprite0 whenever sprite1 is enabled.

	 *

	 * All other plane enable sequences appear immune to this problem.

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −2
Original line number Diff line number Diff line
@@ -243,7 +243,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 
	for_each_dsi_phy(phy, intel_dsi->phys) {

		/*

		 * Program voltage swing and pre-emphasis level values as per

		 * table in BSPEC under DDI buffer programing

		 * table in BSPEC under DDI buffer programming.

		 */

		mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;

		val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
@@ -961,7 +961,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
	for_each_dsi_port(port, intel_dsi->ports) {

		dsi_trans = dsi_port_to_transcoder(port);

		/*

		 * FIXME: Programing this by assuming progressive mode, since

		 * FIXME: Programming this by assuming progressive mode, since

		 * non-interlaced info from VBT is not saved inside

		 * struct drm_display_mode.

		 * For interlace mode: program required pixel minus 2

drivers/gpu/drm/i915/display/intel_audio.c

+2 −2
Original line number Diff line number Diff line
@@ -567,7 +567,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder, 
		     AUDIO_ELD_VALID(cpu_transcoder), 0);



	/*

	 * The audio componenent is used to convey the ELD

	 * The audio component is used to convey the ELD

	 * instead using of the hardware ELD buffer.

	 */
@@ -665,7 +665,7 @@ static void ibx_audio_codec_enable(struct intel_encoder *encoder, 
		     IBX_ELD_VALID(port), 0);



	/*

	 * The audio componenent is used to convey the ELD

	 * The audio component is used to convey the ELD

	 * instead using of the hardware ELD buffer.

	 */

drivers/gpu/drm/i915/display/intel_cdclk.c

+1 −1
Original line number Diff line number Diff line
@@ -2250,7 +2250,7 @@ static void bxt_sanitize_cdclk(struct intel_display *display) 


	/*

	 * Let's ignore the pipe field, since BIOS could have configured the

	 * dividers both synching to an active pipe, or asynchronously

	 * dividers both syncing to an active pipe, or asynchronously

	 * (PIPE_NONE).

	 */

	cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);