Commit c581f8c2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v6.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control fixes from Linus Walleij:

 - A series of IRQ and behaviour stabilization fixes for the CY8C95x0
   pin control expander

 - A print format fix for the generic debugfs output

* tag 'pinctrl-v6.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: pinconf-generic: Print unsigned value if a format is registered
  pinctrl: cy8c95x0: Respect IRQ trigger settings from firmware
  pinctrl: cy8c95x0: Rename PWMSEL to SELPWM
  pinctrl: cy8c95x0: Enable regmap locking for debug
  pinctrl: cy8c95x0: Avoid accessing reserved registers
  pinctrl: cy8c95x0: Fix off-by-one in the regmap range settings
parents a64dcfb4 0af4c120

drivers/pinctrl/pinconf-generic.c

+4 −4
Original line number Diff line number Diff line
@@ -89,12 +89,12 @@ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, 
		seq_puts(s, items[i].display);

		/* Print unit if available */

		if (items[i].has_arg) {

			seq_printf(s, " (0x%x",

				   pinconf_to_config_argument(config));

			u32 val = pinconf_to_config_argument(config);



			if (items[i].format)

				seq_printf(s, " %s)", items[i].format);

				seq_printf(s, " (%u %s)", val, items[i].format);

			else

				seq_puts(s, ")");

				seq_printf(s, " (0x%x)", val);

		}

	}

}

drivers/pinctrl/pinctrl-cy8c95x0.c

+25 −17
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ 
#define CY8C95X0_PORTSEL	0x18

/* Port settings, write PORTSEL first */

#define CY8C95X0_INTMASK	0x19

#define CY8C95X0_PWMSEL		0x1A

#define CY8C95X0_SELPWM		0x1A

#define CY8C95X0_INVERT		0x1B

#define CY8C95X0_DIRECTION	0x1C

/* Drive mode register change state on writing '1' */
@@ -328,14 +328,14 @@ static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) 
static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)

{

	/*

	 * Only 12 registers are present per port (see Table 6 in the

	 * datasheet).

	 * Only 12 registers are present per port (see Table 6 in the datasheet).

	 */

	if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) < 12)

		return true;

	if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12)

		return false;



	switch (reg) {

	case 0x24 ... 0x27:

	case 0x31 ... 0x3f:

		return false;

	default:

		return true;
@@ -344,8 +344,11 @@ static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) 


static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)

{

	if (reg >= CY8C95X0_VIRTUAL)

		return true;

	/*

	 * Only 12 registers are present per port (see Table 6 in the datasheet).

	 */

	if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12)

		return false;



	switch (reg) {

	case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
@@ -353,6 +356,7 @@ static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) 
	case CY8C95X0_DEVID:

		return false;

	case 0x24 ... 0x27:

	case 0x31 ... 0x3f:

		return false;

	default:

		return true;
@@ -365,8 +369,8 @@ static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) 
	case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):

	case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):

	case CY8C95X0_INTMASK:

	case CY8C95X0_SELPWM:

	case CY8C95X0_INVERT:

	case CY8C95X0_PWMSEL:

	case CY8C95X0_DIRECTION:

	case CY8C95X0_DRV_PU:

	case CY8C95X0_DRV_PD:
@@ -395,7 +399,7 @@ static bool cy8c95x0_muxed_register(unsigned int reg) 
{

	switch (reg) {

	case CY8C95X0_INTMASK:

	case CY8C95X0_PWMSEL:

	case CY8C95X0_SELPWM:

	case CY8C95X0_INVERT:

	case CY8C95X0_DIRECTION:

	case CY8C95X0_DRV_PU:
@@ -466,7 +470,11 @@ static const struct regmap_config cy8c9520_i2c_regmap = { 
	.max_register = 0,		/* Updated at runtime */

	.num_reg_defaults_raw = 0,	/* Updated at runtime */

	.use_single_read = true,	/* Workaround for regcache bug */

#if IS_ENABLED(CONFIG_DEBUG_PINCTRL)

	.disable_locking = false,

#else

	.disable_locking = true,

#endif

};



static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip,
@@ -789,7 +797,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, 
		reg = CY8C95X0_DIRECTION;

		break;

	case PIN_CONFIG_MODE_PWM:

		reg = CY8C95X0_PWMSEL;

		reg = CY8C95X0_SELPWM;

		break;

	case PIN_CONFIG_OUTPUT:

		reg = CY8C95X0_OUTPUT;
@@ -868,7 +876,7 @@ static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, 
		reg = CY8C95X0_DRV_PP_FAST;

		break;

	case PIN_CONFIG_MODE_PWM:

		reg = CY8C95X0_PWMSEL;

		reg = CY8C95X0_SELPWM;

		break;

	case PIN_CONFIG_OUTPUT_ENABLE:

		return cy8c95x0_pinmux_direction(chip, off, !arg);
@@ -1153,7 +1161,7 @@ static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file * 
	bitmap_zero(mask, MAX_LINE);

	__set_bit(pin, mask);



	if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {

	if (cy8c95x0_read_regs_mask(chip, CY8C95X0_SELPWM, pwm, mask)) {

		seq_puts(s, "not available");

		return;

	}
@@ -1198,7 +1206,7 @@ static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bo 
	u8 port = cypress_get_port(chip, off);

	u8 bit = cypress_get_pin_mask(chip, off);



	return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode ? bit : 0);

	return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode ? bit : 0);

}



static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
@@ -1347,7 +1355,7 @@ static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) 


	ret = devm_request_threaded_irq(chip->dev, irq,

					NULL, cy8c95x0_irq_handler,

					IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,

					IRQF_ONESHOT | IRQF_SHARED,

					dev_name(chip->dev), chip);

	if (ret) {

		dev_err(chip->dev, "failed to request irq %d\n", irq);
@@ -1438,15 +1446,15 @@ static int cy8c95x0_probe(struct i2c_client *client) 
	switch (chip->tpin) {

	case 20:

		strscpy(chip->name, cy8c95x0_id[0].name);

		regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE;

		regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE - 1;

		break;

	case 40:

		strscpy(chip->name, cy8c95x0_id[1].name);

		regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE;

		regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE - 1;

		break;

	case 60:

		strscpy(chip->name, cy8c95x0_id[2].name);

		regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE;

		regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE - 1;

		break;

	default:

		return -ENODEV;