Commit c5a332f9 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: resolve correct MALL size for dcn401 



[WHY]
Code for dcn401 to calculate available MALL size for display was shared
with dcn32 and did not provide the correct result for all ASICs.

[HOW]
Add dcn401 specific function to properly calculate the available MALL
for display.

Reviewed-by: default avatarChris Park <chris.park@amd.com>
Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 668d6808

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

+4 −0
Original line number Diff line number Diff line
@@ -1990,6 +1990,10 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned 
		return 0;

	}



	if (dc->caps.max_cab_allocation_bytes == 0) {

		return 0xffffffff;

	}



	/* add 2 lines for worst case alignment */

	cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

+24 −3
Original line number Diff line number Diff line
@@ -1704,6 +1704,29 @@ static int dcn401_get_power_profile(const struct dc_state *context) 
	return dpm_level;

}



static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans)

{

	unsigned int num_available_chans = 1;



	/* channels for MALL must be a power of 2 */

	while (num_chans > 1) {

		num_available_chans = (num_available_chans << 1);

		num_chans = (num_chans >> 1);

	}



	/* cannot be odd */

	num_available_chans &= ~1;



	/* clamp to max available channels for MALL per ASIC */

	if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) {

		num_available_chans = num_available_chans > 16 ? 16 : num_available_chans;

	} else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) {

		num_available_chans = num_available_chans > 8 ? 8 : num_available_chans;

	}



	return num_available_chans;

}



static struct resource_funcs dcn401_res_pool_funcs = {

	.destroy = dcn401_destroy_resource_pool,

	.link_enc_create = dcn401_link_encoder_create,
@@ -1812,14 +1835,12 @@ static bool dcn401_resource_construct( 
	dc->caps.min_horizontal_blanking_period = 80;

	dc->caps.dmdata_alloc_size = 2048;

	dc->caps.mall_size_per_mem_channel = 4;

	/* total size = mall per channel * num channels * 1024 * 1024 */

	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;

	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;

	dc->caps.cache_line_size = 64;

	dc->caps.cache_num_ways = 16;



	/* Calculate the available MALL space */

	dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(

	dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(

		dc, dc->ctx->dc_bios->vram_info.num_chans) *

		dc->caps.mall_size_per_mem_channel * 1024 * 1024;

	dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;