Commit c5a87008 authored by Jacopo Mondi's avatar Jacopo Mondi Committed by Geert Uytterhoeven
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clk: renesas: r8a779g0: Add FCPVX clocks 



Add the FCPVX modules clock for Renesas R-Car V4H (R8A779G0) SoC.

Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarJacopo Mondi <jacopo.mondi+renesas@ideasonboard.com>
Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-1-7dc1812585ad@ideasonboard.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 29ebc619

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -238,6 +238,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CP),

	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CP),

	DEF_MOD("tsc",		919,	R8A779G0_CLK_CL16M),

	DEF_MOD("fcpvx0",	1100,	R8A779G0_CLK_S0D1_VIO),

	DEF_MOD("fcpvx1",	1101,	R8A779G0_CLK_S0D1_VIO),

	DEF_MOD("tsn",		2723,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("ssiu",		2926,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("ssi",		2927,	R8A779G0_CLK_S0D6_PER),