Commit c5c2b4b3 authored by Imre Deak's avatar Imre Deak Committed by Tvrtko Ursulin
Browse files

drm/i915/lnl+/tc: Use the cached max lane count value 



Use the cached max lane count value on LNL+, to account for scenarios
where this value is queried after the HW cleared the corresponding pin
assignment value in the TCSS_DDI_STATUS register after the sink got
disconnected.

For consistency, follow-up changes will use the cached max lane count
value on other platforms as well and will also cache the pin assignment
value in a similar way.

Cc: stable@vger.kernel.org # v6.8+
Reported-by: default avatarCharlton Lin <charlton.lin@intel.com>
Tested-by: default avatarKhaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/20250811080152.906216-5-imre.deak@intel.com


(cherry picked from commit afc4e843)
Signed-off-by: default avatarTvrtko Ursulin <tursulin@ursulin.net>
parent c87514a0

drivers/gpu/drm/i915/display/intel_tc.c

+5 −1
Original line number Diff line number Diff line
@@ -395,12 +395,16 @@ static void read_pin_configuration(struct intel_tc_port *tc) 


int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)

{

	struct intel_display *display = to_intel_display(dig_port);

	struct intel_tc_port *tc = to_tc_port(dig_port);



	if (!intel_encoder_is_tc(&dig_port->base))

		return 4;



	if (DISPLAY_VER(display) < 20)

		return get_max_lane_count(tc);



	return tc->max_lane_count;

}



void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,