Commit c5d50457 authored by Kajol Jain's avatar Kajol Jain Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events power10: Update JSON/events 



Update JSON/events for power10 platform with additional events.

Reviewed-by: default avatarIan Rogers <irogers@google.com>
Signed-off-by: default avatarKajol Jain <kjain@linux.ibm.com>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Disha Goel <disgoel@linux.vnet.ibm.com>
Cc: Hari Bathini <hbathini@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lore.kernel.org/r/20240827053206.538814-1-kjain@linux.ibm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 7bedcbae

tools/perf/pmu-events/arch/powerpc/power10/datasource.json

+25 −0
Original line number Diff line number Diff line
@@ -14,6 +14,31 @@ 
    "EventName": "PM_DATA_FROM_MEMORY",

    "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."

  },

  {

    "EventCode": "0x0000004080",

    "EventName": "PM_INST_FROM_L1",

    "BriefDescription": "An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched."

  },

  {

    "EventCode": "0x000000026080",

    "EventName": "PM_L2_LD_MISS",

    "BriefDescription": "All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2."

  },

  {

    "EventCode": "0x000000026880",

    "EventName": "PM_L2_ST_MISS",

    "BriefDescription": "All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2."

  },

  {

    "EventCode": "0x010000046880",

    "EventName": "PM_L2_ST_HIT",

    "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2."

  },

  {

    "EventCode": "0x000000036880",

    "EventName": "PM_L2_INST_MISS",

    "BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2."

  },

  {

    "EventCode": "0x000300000000C040",

    "EventName": "PM_INST_FROM_L2",

tools/perf/pmu-events/arch/powerpc/power10/frontend.json

+10 −0
Original line number Diff line number Diff line
@@ -93,5 +93,15 @@ 
    "EventCode": "0x400FC",

    "EventName": "PM_ITLB_MISS",

    "BriefDescription": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses."

  },

  {

    "EventCode": "0x00000040B8",

    "EventName": "PM_PRED_BR_TKN_COND_DIR",

    "BriefDescription": "A conditional branch finished with correctly predicted direction. Resolved taken."

  },

  {

    "EventCode": "0x00000048B8",

    "EventName": "PM_PRED_BR_NTKN_COND_DIR",

    "BriefDescription": "A conditional branch finished with correctly predicted direction. Resolved not taken."

  }

]

tools/perf/pmu-events/arch/powerpc/power10/pmc.json

+5 −0
Original line number Diff line number Diff line
@@ -104,6 +104,11 @@ 
    "EventName": "PM_RUN_CYC",

    "BriefDescription": "Processor cycles gated by the run latch."

  },

  {

    "EventCode": "0x200F8",

    "EventName": "PM_EXT_INT",

    "BriefDescription": "Cycles an external interrupt was active."

  },

  {

    "EventCode": "0x30010",

    "EventName": "PM_PMC2_OVERFLOW",