Commit c5fb82d1 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2025-12-19' of... 

Merge tag 'drm-intel-next-2025-12-19' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

Beyond Display related:
 - Switch to use kernel standard fault injection in i915 (Juha-Pekka)

 Display uAPI related:
 - Display uapi vs. hw state fixes (Ville)
 - Expose sharpness only if num_scalers is >= 2 (Nemesa)

 Display related:
 - More display driver refactor and clean-ups, specially towards separation (Jani)
 - Add initial support Xe3p_LPD for NVL (Gustavo, Sai, )
 - BMG FBC W/a (Vinod)
 - RPM fix (Dibin)
 - Add MTL+ platforms to support dpll framework (Mika, Imre)
 - Other PLL related fixes (Imre)
 - Fix DIMM_S DRAM decoding on ICL (Ville)
 - Async flip refactor (Ville, Jouni)
 - Go back to using AUX interrupts (Ville)
 - Reduce severity of failed DII FEC enabling (Grzelak)
 - Enable system cache support for FBC (Vinod)
 - Move PSR/Panel Replay sink data into intel_connector and other PSR changes (Jouni)
 - Detect AuxCCS support via display parent interface (Tvrtko)
 - Clean up link BW/DSC slice config computation(Imre)
 - Toggle powerdown states for C10 on HDMI (Gustavo)
 - Add parent interface for PC8 forcewake tricks (Ville)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/aUW3bVDdE63aSFOJ@intel.com
parents 7bc0f871 35ec7128

drivers/gpu/drm/display/drm_dp_helper.c

+66 −37
Original line number Diff line number Diff line
@@ -2705,61 +2705,90 @@ u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 
EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);



/**

 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count

 * supported by the DSC sink.

 * @dsc_dpcd: DSC capabilities from DPCD

 * @is_edp: true if its eDP, false for DP

 * drm_dp_dsc_slice_count_to_mask() - Convert a slice count to a slice count mask

 * @slice_count: slice count

 *

 * Read the slice capabilities DPCD register from DSC sink to get

 * the maximum slice count supported. This is used to populate

 * the DSC parameters in the &struct drm_dsc_config by the driver.

 * Driver creates an infoframe using these parameters to populate

 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC

 * infoframe using the helper function drm_dsc_pps_infoframe_pack()

 * Convert @slice_count to a slice count mask.

 *

 * Returns the slice count mask.

 */

u32 drm_dp_dsc_slice_count_to_mask(int slice_count)

{

	return BIT(slice_count - 1);

}

EXPORT_SYMBOL(drm_dp_dsc_slice_count_to_mask);



/**

 * drm_dp_dsc_sink_slice_count_mask() - Get the mask of valid DSC sink slice counts

 * @dsc_dpcd: the sink's DSC DPCD capabilities

 * @is_edp: %true for an eDP sink

 *

 * Get the mask of supported slice counts from the sink's DSC DPCD register.

 *

 * Returns:

 * Maximum slice count supported by DSC sink or 0 its invalid

 * Mask of slice counts supported by the DSC sink:

 * - > 0: bit#0,1,3,5..,23 set if the sink supports 1,2,4,6..,24 slices

 * - 0:   if the sink doesn't support any slices

 */

u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],

u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],

				     bool is_edp)

{

	u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];

	u32 mask = 0;



	if (is_edp) {

		/* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */

		if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)

			return 4;

		if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)

			return 2;

		if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)

			return 1;

	} else {

	if (!is_edp) {

		/* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */

		u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];



		if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)

			return 24;

			mask |= drm_dp_dsc_slice_count_to_mask(24);

		if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)

			return 20;

			mask |= drm_dp_dsc_slice_count_to_mask(20);

		if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)

			return 16;

			mask |= drm_dp_dsc_slice_count_to_mask(16);

	}



	/* DP, eDP v1.5+ */

	if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)

			return 12;

		mask |= drm_dp_dsc_slice_count_to_mask(12);

	if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)

			return 10;

		mask |= drm_dp_dsc_slice_count_to_mask(10);

	if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)

			return 8;

		mask |= drm_dp_dsc_slice_count_to_mask(8);

	if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)

			return 6;

		mask |= drm_dp_dsc_slice_count_to_mask(6);

	/* DP, eDP v1.4+ */

	if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)

			return 4;

		mask |= drm_dp_dsc_slice_count_to_mask(4);

	if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)

			return 2;

		mask |= drm_dp_dsc_slice_count_to_mask(2);

	if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)

			return 1;

		mask |= drm_dp_dsc_slice_count_to_mask(1);



	return mask;

}

EXPORT_SYMBOL(drm_dp_dsc_sink_slice_count_mask);



	return 0;

/**

 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count

 * supported by the DSC sink.

 * @dsc_dpcd: DSC capabilities from DPCD

 * @is_edp: true if its eDP, false for DP

 *

 * Read the slice capabilities DPCD register from DSC sink to get

 * the maximum slice count supported. This is used to populate

 * the DSC parameters in the &struct drm_dsc_config by the driver.

 * Driver creates an infoframe using these parameters to populate

 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC

 * infoframe using the helper function drm_dsc_pps_infoframe_pack()

 *

 * Returns:

 * Maximum slice count supported by DSC sink or 0 its invalid

 */

u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],

				   bool is_edp)

{

	return fls(drm_dp_dsc_sink_slice_count_mask(dsc_dpcd, is_edp));

}

EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);

drivers/gpu/drm/i915/Makefile

+12 −8
Original line number Diff line number Diff line
@@ -27,7 +27,10 @@ i915-y += \ 
	i915_config.o \

	i915_driver.o \

	i915_drm_client.o \

	i915_edram.o \

	i915_freq.o \

	i915_getparam.o \

	i915_gmch.o \

	i915_ioctl.o \

	i915_irq.o \

	i915_mitigations.o \
@@ -54,12 +57,6 @@ i915-y += \ 
	vlv_iosf_sb.o \

	vlv_suspend.o



# core peripheral code

i915-y += \

	soc/intel_dram.o \

	soc/intel_gmch.o \

	soc/intel_rom.o



# core library code

i915-y += \

	i915_memcpy.o \
@@ -77,6 +74,12 @@ i915-$(CONFIG_DEBUG_FS) += \ 
i915-$(CONFIG_PERF_EVENTS) += \

	i915_pmu.o



# core display adaptation

i915-y += \

	i915_display_pc8.o \

	i915_hdcp_gsc.o \

	i915_panic.o



# "Graphics Technology" (aka we talk to the gpu)

gt-y += \

	gt/gen2_engine_cs.o \
@@ -267,6 +270,7 @@ i915-y += \ 
	display/intel_dpll_mgr.o \

	display/intel_dpt.o \

	display/intel_dpt_common.o \

	display/intel_dram.o \

	display/intel_drrs.o \

	display/intel_dsb.o \

	display/intel_dsb_buffer.o \
@@ -280,7 +284,6 @@ i915-y += \ 
	display/intel_frontbuffer.o \

	display/intel_global_state.o \

	display/intel_hdcp.o \

	display/intel_hdcp_gsc.o \

	display/intel_hdcp_gsc_message.o \

	display/intel_hotplug.o \

	display/intel_hotplug_irq.o \
@@ -292,7 +295,7 @@ i915-y += \ 
	display/intel_modeset_setup.o \

	display/intel_modeset_verify.o \

	display/intel_overlay.o \

	display/intel_panic.o \

	display/intel_parent.o \

	display/intel_pch.o \

	display/intel_pch_display.o \

	display/intel_pch_refclk.o \
@@ -301,6 +304,7 @@ i915-y += \ 
	display/intel_pmdemand.o \

	display/intel_psr.o \

	display/intel_quirks.o \

	display/intel_rom.o \

	display/intel_sbi.o \

	display/intel_sprite.o \

	display/intel_sprite_uapi.o \

drivers/gpu/drm/i915/display/g4x_dp.c

+2 −3
Original line number Diff line number Diff line
@@ -302,7 +302,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 
{

	struct intel_display *display = to_intel_display(encoder);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	intel_wakeref_t wakeref;

	struct ref_tracker *wakeref;

	bool ret;



	wakeref = intel_display_power_get_if_enabled(display,
@@ -684,12 +684,11 @@ static void intel_enable_dp(struct intel_atomic_state *state, 
	struct intel_display *display = to_intel_display(state);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u32 dp_reg = intel_de_read(display, intel_dp->output_reg);

	intel_wakeref_t wakeref;



	if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))

		return;



	with_intel_pps_lock(intel_dp, wakeref) {

	with_intel_pps_lock(intel_dp) {

		if (display->platform.valleyview || display->platform.cherryview)

			vlv_pps_port_enable_unlocked(encoder, pipe_config);

drivers/gpu/drm/i915/display/g4x_hdmi.c

+1 −1
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 
{

	struct intel_display *display = to_intel_display(encoder);

	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	intel_wakeref_t wakeref;

	struct ref_tracker *wakeref;

	bool ret;



	wakeref = intel_display_power_get_if_enabled(display,

drivers/gpu/drm/i915/display/i9xx_plane.c

+4 −5
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 
#include "intel_fb.h"

#include "intel_fbc.h"

#include "intel_frontbuffer.h"

#include "intel_panic.h"

#include "intel_plane.h"

#include "intel_sprite.h"
@@ -134,7 +133,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display, 
					enum i9xx_plane_id i9xx_plane)

{

	if (i9xx_plane_has_fbc(display, i9xx_plane))

		return display->fbc[INTEL_FBC_A];

		return display->fbc.instances[INTEL_FBC_A];

	else

		return NULL;

}
@@ -724,7 +723,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 
	struct intel_display *display = to_intel_display(plane);

	enum intel_display_power_domain power_domain;

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	intel_wakeref_t wakeref;

	struct ref_tracker *wakeref;

	bool ret;

	u32 val;
@@ -819,7 +818,7 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, 
{

	struct intel_display *display = to_intel_display(plane);



	if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))

	if (intel_plane_can_async_flip(plane, fb->format, fb->modifier))

		return 256 * 1024;



	/* FIXME undocumented so not sure what's actually needed */
@@ -843,7 +842,7 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, 
{

	struct intel_display *display = to_intel_display(plane);



	if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier))

	if (intel_plane_can_async_flip(plane, fb->format, fb->modifier))

		return 256 * 1024;



	if (intel_scanout_needs_vtd_wa(display))