Commit c63fe2e7 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/acr: add loaders for currently available LS firmware images 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 67e7c6cf

drivers/gpu/drm/nouveau/include/nvfw/fw.h

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+28 −0
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/* SPDX-License-Identifier: MIT */

#ifndef __NVFW_FW_H__

#define __NVFW_FW_H__

#include <core/os.h>

struct nvkm_subdev;



struct nvfw_bin_hdr {

	u32 bin_magic;

	u32 bin_ver;

	u32 bin_size;

	u32 header_offset;

	u32 data_offset;

	u32 data_size;

};



const struct nvfw_bin_hdr *nvfw_bin_hdr(struct nvkm_subdev *, const void *);



struct nvfw_bl_desc {

	u32 start_tag;

	u32 dmem_load_off;

	u32 code_off;

	u32 code_size;

	u32 data_off;

	u32 data_size;

};



const struct nvfw_bl_desc *nvfw_bl_desc(struct nvkm_subdev *, const void *);

#endif

drivers/gpu/drm/nouveau/include/nvfw/ls.h

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/* SPDX-License-Identifier: MIT */

#ifndef __NVFW_LS_H__

#define __NVFW_LS_H__

#include <core/os.h>

struct nvkm_subdev;



struct nvfw_ls_desc_head {

	u32 descriptor_size;

	u32 image_size;

	u32 tools_version;

	u32 app_version;

	char date[64];

	u32 bootloader_start_offset;

	u32 bootloader_size;

	u32 bootloader_imem_offset;

	u32 bootloader_entry_point;

	u32 app_start_offset;

	u32 app_size;

	u32 app_imem_offset;

	u32 app_imem_entry;

	u32 app_dmem_offset;

	u32 app_resident_code_offset;

	u32 app_resident_code_size;

	u32 app_resident_data_offset;

	u32 app_resident_data_size;

};



struct nvfw_ls_desc {

	struct nvfw_ls_desc_head head;

	u32 nb_overlays;

	struct {

		u32 start;

		u32 size;

	} load_ovl[64];

	u32 compressed;

};



const struct nvfw_ls_desc *nvfw_ls_desc(struct nvkm_subdev *, const void *);



struct nvfw_ls_desc_v1 {

	struct nvfw_ls_desc_head head;

	u32 nb_imem_overlays;

	u32 nb_dmem_overlays;

	struct {

		u32 start;

		u32 size;

	} load_ovl[64];

	u32 compressed;

};



const struct nvfw_ls_desc_v1 *

nvfw_ls_desc_v1(struct nvkm_subdev *, const void *);

#endif

drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h

+6 −0
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@@ -11,6 +11,12 @@ int nvkm_firmware_get(const struct nvkm_subdev *, const char *fwname, 
		      const struct firmware **);

void nvkm_firmware_put(const struct firmware *);



int nvkm_firmware_load_blob(const struct nvkm_subdev *subdev, const char *path,

			    const char *name, int ver, struct nvkm_blob *);

int nvkm_firmware_load_name(const struct nvkm_subdev *subdev, const char *path,

			    const char *name, int ver,

			    const struct firmware **);



#define nvkm_firmware_load(s,l,o,p...) ({                                      \

	struct nvkm_subdev *_s = (s);                                          \

	const char *_opts = (o);                                               \

drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h

+54 −0
Original line number Diff line number Diff line
@@ -5,9 +5,21 @@ 
#include <core/subdev.h>

struct nvkm_falcon;



enum nvkm_acr_lsf_id {

	NVKM_ACR_LSF_PMU = 0,

	NVKM_ACR_LSF_GSPLITE = 1,

	NVKM_ACR_LSF_FECS = 2,

	NVKM_ACR_LSF_GPCCS = 3,

	NVKM_ACR_LSF_NVDEC = 4,

	NVKM_ACR_LSF_SEC2 = 7,

	NVKM_ACR_LSF_MINION = 10,

};



struct nvkm_acr {

	const struct nvkm_acr_func *func;

	struct nvkm_subdev subdev;



	struct list_head lsfw;

};



int gm200_acr_new(struct nvkm_device *, int, struct nvkm_acr **);
@@ -15,4 +27,46 @@ int gm20b_acr_new(struct nvkm_device *, int, struct nvkm_acr **); 
int gp102_acr_new(struct nvkm_device *, int, struct nvkm_acr **);

int gp108_acr_new(struct nvkm_device *, int, struct nvkm_acr **);

int gp10b_acr_new(struct nvkm_device *, int, struct nvkm_acr **);



struct nvkm_acr_lsfw {

	const struct nvkm_acr_lsf_func *func;

	struct nvkm_falcon *falcon;

	enum nvkm_acr_lsf_id id;



	struct list_head head;



	struct nvkm_blob img;



	const struct firmware *sig;



	u32 bootloader_size;

	u32 bootloader_imem_offset;



	u32 app_size;

	u32 app_start_offset;

	u32 app_imem_entry;

	u32 app_resident_code_offset;

	u32 app_resident_code_size;

	u32 app_resident_data_offset;

	u32 app_resident_data_size;



	u32 ucode_size;

	u32 data_size;

};



struct nvkm_acr_lsf_func {

};



int

nvkm_acr_lsfw_load_sig_image_desc(struct nvkm_subdev *, struct nvkm_falcon *,

				  enum nvkm_acr_lsf_id, const char *path,

				  int ver, const struct nvkm_acr_lsf_func *);

int

nvkm_acr_lsfw_load_sig_image_desc_v1(struct nvkm_subdev *, struct nvkm_falcon *,

				     enum nvkm_acr_lsf_id, const char *path,

				     int ver, const struct nvkm_acr_lsf_func *);

int

nvkm_acr_lsfw_load_bl_inst_data_sig(struct nvkm_subdev *, struct nvkm_falcon *,

				    enum nvkm_acr_lsf_id, const char *path,

				    int ver, const struct nvkm_acr_lsf_func *);

#endif

drivers/gpu/drm/nouveau/nvkm/Kbuild

+1 −0
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# SPDX-License-Identifier: MIT

include $(src)/nvkm/core/Kbuild

include $(src)/nvkm/nvfw/Kbuild

include $(src)/nvkm/falcon/Kbuild

include $(src)/nvkm/subdev/Kbuild

include $(src)/nvkm/engine/Kbuild