Commit c661219c authored by Timur Kristóf's avatar Timur Kristóf Committed by Alex Deucher
Browse files

drm/amdgpu: Power up UVD 3 for FW validation (v2) 



Unlike later versions, UVD 3 has firmware validation.
For this to work, the UVD should be powered up correctly.

When DPM is enabled and the display clock is off,
the SMU may choose a power state which doesn't power
the UVD, which can result in failure to initialize UVD.

v2:
Add code comments to explain about the UVD power state
and how UVD clock is turned on/off.

Fixes: b38f3e80 ("drm amdgpu: SI UVD v3_1 (v2)")
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarTimur Kristóf <timur.kristof@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 85705b18

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

+25 −4
Original line number Diff line number Diff line
@@ -623,7 +623,22 @@ static void uvd_v3_1_enable_mgcg(struct amdgpu_device *adev, 
 *

 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.

 *

 * Initialize the hardware, boot up the VCPU and do some testing

 * Initialize the hardware, boot up the VCPU and do some testing.

 *

 * On SI, the UVD is meant to be used in a specific power state,

 * or alternatively the driver can manually enable its clock.

 * In amdgpu we use the dedicated UVD power state when DPM is enabled.

 * Calling amdgpu_dpm_enable_uvd makes DPM select the UVD power state

 * for the SMU and afterwards enables the UVD clock.

 * This is automatically done by amdgpu_uvd_ring_begin_use when work

 * is submitted to the UVD ring. Here, we have to call it manually

 * in order to power up UVD before firmware validation.

 *

 * Note that we must not disable the UVD clock here, as that would

 * cause the ring test to fail. However, UVD is powered off

 * automatically after the ring test: amdgpu_uvd_ring_end_use calls

 * the UVD idle work handler which will disable the UVD clock when

 * all fences are signalled.

 */

static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block)

{
@@ -633,6 +648,15 @@ static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) 
	int r;



	uvd_v3_1_mc_resume(adev);

	uvd_v3_1_enable_mgcg(adev, true);



	/* Make sure UVD is powered during FW validation.

	 * It's going to be automatically powered off after the ring test.

	 */

	if (adev->pm.dpm_enabled)

		amdgpu_dpm_enable_uvd(adev, true);

	else

		amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);



	r = uvd_v3_1_fw_validate(adev);

	if (r) {
@@ -640,9 +664,6 @@ static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) 
		return r;

	}



	uvd_v3_1_enable_mgcg(adev, true);

	amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);



	uvd_v3_1_start(adev);



	r = amdgpu_ring_test_helper(ring);