Commit c6929644 authored by Ravikanth Tuniki's avatar Ravikanth Tuniki Committed by Paolo Abeni
Browse files

dt-bindings: net: xlnx,axi-ethernet: Add missing reg minItems



Add missing reg minItems as based on current binding document
only ethernet MAC IO space is a supported configuration.

There is a bug in schema, current examples contain 64-bit
addressing as well as 32-bit addressing. The schema validation
does pass incidentally considering one 64-bit reg address as
two 32-bit reg address entries. If we change axi_ethernet_eth1
example node reg addressing to 32-bit schema validation reports:

Documentation/devicetree/bindings/net/xlnx,axi-ethernet.example.dtb:
ethernet@40000000: reg: [[1073741824, 262144]] is too short

To fix it add missing reg minItems constraints and to make things clearer
stick to 32-bit addressing in examples.

Fixes: cbb1ca6d ("dt-bindings: net: xlnx,axi-ethernet: convert bindings document to yaml")
Signed-off-by: default avatarRavikanth Tuniki <ravikanth.tuniki@amd.com>
Signed-off-by: default avatarRadhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/1727723615-2109795-1-git-send-email-radhey.shyam.pandey@amd.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent b63ad06d
Loading
Loading
Loading
Loading
+2 −1
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ properties:
      and length of the AXI DMA controller IO space, unless
      axistream-connected is specified, in which case the reg
      attribute of the node referenced by it is used.
    minItems: 1
    maxItems: 2

  interrupts:
@@ -181,7 +182,7 @@ examples:
        clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
        clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
        phy-mode = "mii";
        reg = <0x00 0x40000000 0x00 0x40000>;
        reg = <0x40000000 0x40000>;
        xlnx,rxcsum = <0x2>;
        xlnx,rxmem = <0x800>;
        xlnx,txcsum = <0x2>;