Commit c6fa06fc authored by Jinzhou Su's avatar Jinzhou Su Committed by Alex Deucher
Browse files

drm/amdgpu/psp_v15_0_8: Add get ras capability 



Add get ras capability for psp 15.0.8.

v2:Remove APU type check and IP version check.

Signed-off-by: default avatarJinzhou Su <jinzhou.su@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent da8c2760

drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c

+21 −0
Original line number Diff line number Diff line
@@ -187,6 +187,26 @@ static void psp_v15_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value) 
		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);

}



static bool psp_v15_0_8_get_ras_capability(struct psp_context *psp)

{

	struct amdgpu_device *adev = psp->adev;

	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

	u32 reg_data;



	/* query ras cap should be done from host side */

	if (amdgpu_sriov_vf(adev))

		return false;



	if (!con)

		return false;



	reg_data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_127);

	adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));

	con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;



	return true;

}



static int psp_v15_0_8_get_fw_type(struct amdgpu_firmware_info *ucode,

				   enum psp_gfx_fw_type *type)

{
@@ -334,6 +354,7 @@ static const struct psp_funcs psp_v15_0_8_funcs = { 
	.ring_get_wptr = psp_v15_0_8_ring_get_wptr,

	.ring_set_wptr = psp_v15_0_8_ring_set_wptr,

	.get_fw_type = psp_v15_0_8_get_fw_type,

	.get_ras_capability = psp_v15_0_8_get_ras_capability,

};



void psp_v15_0_8_set_psp_funcs(struct psp_context *psp)