Commit c7062be3 authored by Relja Vojvodic's avatar Relja Vojvodic Committed by Alex Deucher
Browse files

drm/amd/display: Correct DSC padding accounting 



[WHY]
- After the addition of all OVT patches, DSC padding was being accounted
  for multiple times, effectively doubling the padding
- This caused compliance failures or corruption

[HOW]
- Add padding to DSC pic width when required by HW, and do not re-add
  when calculating reg values
- Do not add padding when computing PPS values, and instead track padding
  separately to add when calculating slice width values

Reviewed-by: default avatarChris Park <chris.park@amd.com>
Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarRelja Vojvodic <rvojvodi@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a574f53e

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

+1 −1
Original line number Diff line number Diff line
@@ -108,7 +108,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 
		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);

		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;

		dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;

		dsc_cfg.dsc_padding = 0;



		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

+1 −1
Original line number Diff line number Diff line
@@ -1061,7 +1061,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 
		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);

		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;

		dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;

		dsc_cfg.dsc_padding = 0;



		if (should_use_dto_dscclk)

			dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

+1 −1
Original line number Diff line number Diff line
@@ -364,7 +364,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 
		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);

		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;

		dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;

		dsc_cfg.dsc_padding = 0;



		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

+2 −1
Original line number Diff line number Diff line
@@ -841,7 +841,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 
		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);

		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;

		dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;

		dsc_cfg.dsc_padding = 0;



		if (should_use_dto_dscclk)

			dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);
@@ -857,6 +857,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 
		}

		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;

		dsc_cfg.pic_width *= opp_cnt;

		dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;



		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

+3 −3
Original line number Diff line number Diff line
@@ -1660,8 +1660,8 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 
		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)

			continue;



		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left

				+ stream->timing.h_border_right) / opp_cnt;

		dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding

				+ stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;

		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top

				+ stream->timing.v_border_bottom;

		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
@@ -1669,7 +1669,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 
		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;

		dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;

		dsc_cfg.dsc_padding = 0;



		if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))

			return false;