Commit c7085d08 authored by Suraj Kandpal's avatar Suraj Kandpal
Browse files

drm/i915/pps: Disable DPLS_GATING around pps sequence 



Disable bit 29 of SCLKGATE_DIS register around pps sequence
when we turn panel power on.

--v2
-Squash two commit together [Jani]
-Use IS_DISPLAY_VER [Jani]
-Fix multiline comment [Jani]

--v3
-Define register in a more appropriate place [Mitul]

--v4
-Register is already defined no need to define it again [Ville]
-Use correct WA number (lineage no.) [Dnyaneshwar]
-Fix the range on which this WA is applied [Dnyaneshwar]

Bspec: 49304
Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: default avatarDnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240813042807.4015214-1-suraj.kandpal@intel.com
parent dd925902

drivers/gpu/drm/i915/display/intel_pps.c

+12 −0
Original line number Diff line number Diff line
@@ -951,6 +951,14 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp) 
		intel_de_posting_read(dev_priv, pp_ctrl_reg);

	}



	/*

	 * WA: 22019252566

	 * Disable DPLS gating around power sequence.

	 */

	if (IS_DISPLAY_VER(dev_priv, 13, 14))

		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,

			     0, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);



	pp |= PANEL_POWER_ON;

	if (!IS_IRONLAKE(dev_priv))

		pp |= PANEL_POWER_RESET;
@@ -961,6 +969,10 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp) 
	wait_panel_on(intel_dp);

	intel_dp->pps.last_power_on = jiffies;



	if (IS_DISPLAY_VER(dev_priv, 13, 14))

		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,

			     PCH_DPLSUNIT_CLOCK_GATE_DISABLE, 0);



	if (IS_IRONLAKE(dev_priv)) {

		pp |= PANEL_POWER_RESET; /* restore panel reset bit */

		intel_de_write(dev_priv, pp_ctrl_reg, pp);