Unverified Commit c74f037d authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "dt-bindings: interrupt-controller: riscv,cpu-intc" 

Kanak Shilledar <kanakshilledar@gmail.com> says:

This series of patches converts the RISC-V CPU interrupt controller to
the newer dt-schema binding.

Patch 1:
This patch is currently at v4 as it has been previously rolled out.
Contains the bindings for the interrupt controller.

Patch 2:
This patch is currently at v4.
Contains the reference to the above interrupt controller. Thus, making
all the RISC-V interrupt controller bindings in a centralized place.

These patches are interdependent.
Fixed the patch address mismatch error by changing DCO to @gmail.com

Kanak Shilledar (3):
  dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
  dt-bindings: riscv: cpus: add ref to interrupt-controller
  dt-bindings: serial: vt8500-uart: convert to json-schema

 .../interrupt-controller/riscv,cpu-intc.txt   | 52 -------------
 .../interrupt-controller/riscv,cpu-intc.yaml  | 73 +++++++++++++++++++
 .../devicetree/bindings/riscv/cpus.yaml       | 21 +-----
 .../bindings/serial/via,vt8500-uart.yaml      | 46 ++++++++++++
 .../bindings/serial/vt8500-uart.txt           | 27 -------
 5 files changed, 120 insertions(+), 99 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
 create mode 100644 Documentation/devicetree/bindings/serial/via,vt8500-uart.yaml
 delete mode 100644 Documentation/devicetree/bindings/serial/vt8500-uart.txt

* b4-shazam-merge:
  dt-bindings: riscv: cpus: add ref to interrupt-controller
  dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema

Link: https://lore.kernel.org/r/20240615021507.122035-1-kanakshilledar@gmail.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 6d8e604c 1f6e2188

Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt

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RISC-V Hart-Level Interrupt Controller (HLIC)

---------------------------------------------



RISC-V cores include Control Status Registers (CSRs) which are local to each

CPU core (HART in RISC-V terminology) and can be read or written by software.

Some of these CSRs are used to control local interrupts connected to the core.

Every interrupt is ultimately routed through a hart's HLIC before it

interrupts that hart.



The RISC-V supervisor ISA manual specifies three interrupt sources that are

attached to every HLIC: software interrupts, the timer interrupt, and external

interrupts.  Software interrupts are used to send IPIs between cores.  The

timer interrupt comes from an architecturally mandated real-time timer that is

controlled via Supervisor Binary Interface (SBI) calls and CSR reads.  External

interrupts connect all other device interrupts to the HLIC, which are routed

via the platform-level interrupt controller (PLIC).



All RISC-V systems that conform to the supervisor ISA specification are

required to have a HLIC with these three interrupt sources present.  Since the

interrupt map is defined by the ISA it's not listed in the HLIC's device tree

entry, though external interrupt controllers (like the PLIC, for example) will

need to define how their interrupts map to the relevant HLICs.  This means

a PLIC interrupt property will typically list the HLICs for all present HARTs

in the system.



Required properties:

- compatible : "riscv,cpu-intc"

- #interrupt-cells : should be <1>.  The interrupt sources are defined by the

  RISC-V supervisor ISA manual, with only the following three interrupts being

  defined for supervisor mode:

    - Source 1 is the supervisor software interrupt, which can be sent by an SBI

      call and is reserved for use by software.

    - Source 5 is the supervisor timer interrupt, which can be configured by

      SBI calls and implements a one-shot timer.

    - Source 9 is the supervisor external interrupt, which chains to all other

      device interrupts.

- interrupt-controller : Identifies the node as an interrupt controller



Furthermore, this interrupt-controller MUST be embedded inside the cpu

definition of the hart whose CSRs control these local interrupts.



An example device tree entry for a HLIC is show below.



	cpu1: cpu@1 {

		compatible = "riscv";

		...

		cpu1-intc: interrupt-controller {

			#interrupt-cells = <1>;

			compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";

			interrupt-controller;

		};

	};

Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: RISC-V Hart-Level Interrupt Controller (HLIC)



description:

  RISC-V cores include Control Status Registers (CSRs) which are local to

  each CPU core (HART in RISC-V terminology) and can be read or written by

  software. Some of these CSRs are used to control local interrupts connected

  to the core. Every interrupt is ultimately routed through a hart's HLIC

  before it interrupts that hart.



  The RISC-V supervisor ISA manual specifies three interrupt sources that are

  attached to every HLIC namely software interrupts, the timer interrupt, and

  external interrupts. Software interrupts are used to send IPIs between

  cores.  The timer interrupt comes from an architecturally mandated real-

  time timer that is controlled via Supervisor Binary Interface (SBI) calls

  and CSR reads. External interrupts connect all other device interrupts to

  the HLIC, which are routed via the platform-level interrupt controller

  (PLIC).



  All RISC-V systems that conform to the supervisor ISA specification are

  required to have a HLIC with these three interrupt sources present.  Since

  the interrupt map is defined by the ISA it's not listed in the HLIC's device

  tree entry, though external interrupt controllers (like the PLIC, for

  example) will need to define how their interrupts map to the relevant HLICs.

  This means a PLIC interrupt property will typically list the HLICs for all

  present HARTs in the system.



maintainers:

  - Palmer Dabbelt <palmer@dabbelt.com>

  - Paul Walmsley <paul.walmsley@sifive.com>



properties:

  compatible:

    oneOf:

      - items:

          - const: andestech,cpu-intc

          - const: riscv,cpu-intc

      - const: riscv,cpu-intc



  interrupt-controller: true



  '#interrupt-cells':

    const: 1

    description: |

      The interrupt sources are defined by the RISC-V supervisor ISA manual,

      with only the following three interrupts being defined for

      supervisor mode:

        - Source 1 is the supervisor software interrupt, which can be sent by

          an SBI call and is reserved for use by software.

        - Source 5 is the supervisor timer interrupt, which can be configured

          by SBI calls and implements a one-shot timer.

        - Source 9 is the supervisor external interrupt, which chains to all

          other device interrupts.



required:

  - compatible

  - '#interrupt-cells'

  - interrupt-controller



additionalProperties: false



examples:

  - |

    interrupt-controller {

        #interrupt-cells = <1>;

        compatible = "riscv,cpu-intc";

        interrupt-controller;

    };

Documentation/devicetree/bindings/riscv/cpus.yaml

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Original line number Diff line number Diff line
@@ -102,26 +102,7 @@ properties: 


  interrupt-controller:

    type: object

    additionalProperties: false

    description: Describes the CPU's local interrupt controller



    properties:

      '#interrupt-cells':

        const: 1



      compatible:

        oneOf:

          - items:

              - const: andestech,cpu-intc

              - const: riscv,cpu-intc

          - const: riscv,cpu-intc



      interrupt-controller: true



    required:

      - '#interrupt-cells'

      - compatible

      - interrupt-controller

    $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#



  cpu-idle-states:

    $ref: /schemas/types.yaml#/definitions/phandle-array