Commit c756441c authored by Junhao He's avatar Junhao He Committed by Arnaldo Carvalho de Melo
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perf vendor events arm64: Drop hip08 PublicDescription if same as BriefDescription 



If BriefDescription and PublicDescription are the same, only
BriefDescription is needed. It will be used for both long and short
format outputs.

Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Signed-off-by: default avatarJunhao He <hejunhao3@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20250418070812.3771441-3-hejunhao3@huawei.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 43fff3e9

tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json

+0 −8
Original line number Diff line number Diff line
@@ -3,56 +3,48 @@ 
	    "ConfigCode": "0x00",

	    "EventName": "flux_wr",

	    "BriefDescription": "DDRC total write operations",

	    "PublicDescription": "DDRC total write operations",

	    "Unit": "hisi_sccl,ddrc"

   },

   {

	    "ConfigCode": "0x01",

	    "EventName": "flux_rd",

	    "BriefDescription": "DDRC total read operations",

	    "PublicDescription": "DDRC total read operations",

	    "Unit": "hisi_sccl,ddrc"

   },

   {

	    "ConfigCode": "0x02",

	    "EventName": "flux_wcmd",

	    "BriefDescription": "DDRC write commands",

	    "PublicDescription": "DDRC write commands",

	    "Unit": "hisi_sccl,ddrc"

   },

   {

	    "ConfigCode": "0x03",

	    "EventName": "flux_rcmd",

	    "BriefDescription": "DDRC read commands",

	    "PublicDescription": "DDRC read commands",

	    "Unit": "hisi_sccl,ddrc"

   },

   {

	    "ConfigCode": "0x04",

	    "EventName": "pre_cmd",

	    "BriefDescription": "DDRC precharge commands",

	    "PublicDescription": "DDRC precharge commands",

	    "Unit": "hisi_sccl,ddrc"

   },

   {

	    "ConfigCode": "0x05",

	    "EventName": "act_cmd",

	    "BriefDescription": "DDRC active commands",

	    "PublicDescription": "DDRC active commands",

	    "Unit": "hisi_sccl,ddrc"

   },

   {

	    "ConfigCode": "0x06",

	    "EventName": "rnk_chg",

	    "BriefDescription": "DDRC rank commands",

	    "PublicDescription": "DDRC rank commands",

	    "Unit": "hisi_sccl,ddrc"

   },

   {

	    "ConfigCode": "0x07",

	    "EventName": "rw_chg",

	    "BriefDescription": "DDRC read and write changes",

	    "PublicDescription": "DDRC read and write changes",

	    "Unit": "hisi_sccl,ddrc"

   }

]

tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json

+0 −10
Original line number Diff line number Diff line
@@ -3,28 +3,24 @@ 
	    "ConfigCode": "0x00",

	    "EventName": "rx_ops_num",

	    "BriefDescription": "The number of all operations received by the HHA",

	    "PublicDescription": "The number of all operations received by the HHA",

	    "Unit": "hisi_sccl,hha"

   },

   {

	    "ConfigCode": "0x01",

	    "EventName": "rx_outer",

	    "BriefDescription": "The number of all operations received by the HHA from another socket",

	    "PublicDescription": "The number of all operations received by the HHA from another socket",

	    "Unit": "hisi_sccl,hha"

   },

   {

	    "ConfigCode": "0x02",

	    "EventName": "rx_sccl",

	    "BriefDescription": "The number of all operations received by the HHA from another SCCL in this socket",

	    "PublicDescription": "The number of all operations received by the HHA from another SCCL in this socket",

	    "Unit": "hisi_sccl,hha"

   },

   {

	    "ConfigCode": "0x03",

	    "EventName": "rx_ccix",

	    "BriefDescription": "Count of the number of operations that HHA has received from CCIX",

	    "PublicDescription": "Count of the number of operations that HHA has received from CCIX",

	    "Unit": "hisi_sccl,hha"

   },

   {
@@ -49,42 +45,36 @@ 
	    "ConfigCode": "0x1c",

	    "EventName": "rd_ddr_64b",

	    "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",

	    "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",

	    "Unit": "hisi_sccl,hha"

   },

   {

	    "ConfigCode": "0x1d",

	    "EventName": "wr_ddr_64b",

	    "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",

	    "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",

	    "Unit": "hisi_sccl,hha"

   },

   {

	    "ConfigCode": "0x1e",

	    "EventName": "rd_ddr_128b",

	    "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",

	    "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",

	    "Unit": "hisi_sccl,hha"

   },

   {

	    "ConfigCode": "0x1f",

	    "EventName": "wr_ddr_128b",

	    "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",

	    "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",

	    "Unit": "hisi_sccl,hha"

   },

   {

	    "ConfigCode": "0x20",

	    "EventName": "spill_num",

	    "BriefDescription": "Count of the number of spill operations that the HHA has sent",

	    "PublicDescription": "Count of the number of spill operations that the HHA has sent",

	    "Unit": "hisi_sccl,hha"

   },

   {

	    "ConfigCode": "0x21",

	    "EventName": "spill_success",

	    "BriefDescription": "Count of the number of successful spill operations that the HHA has sent",

	    "PublicDescription": "Count of the number of successful spill operations that the HHA has sent",

	    "Unit": "hisi_sccl,hha"

   },

   {

tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json

+0 −13
Original line number Diff line number Diff line
@@ -3,91 +3,78 @@ 
	    "ConfigCode": "0x00",

	    "EventName": "rd_cpipe",

	    "BriefDescription": "Total read accesses",

	    "PublicDescription": "Total read accesses",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x01",

	    "EventName": "wr_cpipe",

	    "BriefDescription": "Total write accesses",

	    "PublicDescription": "Total write accesses",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x02",

	    "EventName": "rd_hit_cpipe",

	    "BriefDescription": "Total read hits",

	    "PublicDescription": "Total read hits",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x03",

	    "EventName": "wr_hit_cpipe",

	    "BriefDescription": "Total write hits",

	    "PublicDescription": "Total write hits",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x04",

	    "EventName": "victim_num",

	    "BriefDescription": "l3c precharge commands",

	    "PublicDescription": "l3c precharge commands",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x20",

	    "EventName": "rd_spipe",

	    "BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",

	    "PublicDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x21",

	    "EventName": "wr_spipe",

	    "BriefDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",

	    "PublicDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x22",

	    "EventName": "rd_hit_spipe",

	    "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C",

	    "PublicDescription": "Count of the number of read lines that hits in spipe of this L3C",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x23",

	    "EventName": "wr_hit_spipe",

	    "BriefDescription": "Count of the number of write lines that hits in spipe of this L3C",

	    "PublicDescription": "Count of the number of write lines that hits in spipe of this L3C",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x29",

	    "EventName": "back_invalid",

	    "BriefDescription": "Count of the number of L3C back invalid operations",

	    "PublicDescription": "Count of the number of L3C back invalid operations",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x40",

	    "EventName": "retry_cpu",

	    "BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations",

	    "PublicDescription": "Count of the number of retry that L3C suppresses the CPU operations",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x41",

	    "EventName": "retry_ring",

	    "BriefDescription": "Count of the number of retry that L3C suppresses the ring operations",

	    "PublicDescription": "Count of the number of retry that L3C suppresses the ring operations",

	    "Unit": "hisi_sccl,l3c"

   },

   {

	    "ConfigCode": "0x42",

	    "EventName": "prefetch_drop",

	    "BriefDescription": "Count of the number of prefetch drops from this L3C",

	    "PublicDescription": "Count of the number of prefetch drops from this L3C",

	    "Unit": "hisi_sccl,l3c"

   }

]