Unverified Commit c77bf360 authored by Anup Patel's avatar Anup Patel Committed by Palmer Dabbelt
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tty/serial: Add RISC-V SBI debug console based earlycon



We extend the existing RISC-V SBI earlycon support to use the new
RISC-V SBI debug console extension.

Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Acked-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/20231124070905.1043092-4-apatel@ventanamicro.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent f43fabf4
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+1 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST

config SERIAL_EARLYCON_RISCV_SBI
	bool "Early console using RISC-V SBI"
	depends on RISCV_SBI_V01
	depends on RISCV_SBI
	select SERIAL_CORE
	select SERIAL_CORE_CONSOLE
	select SERIAL_EARLYCON
+24 −3
Original line number Diff line number Diff line
@@ -15,17 +15,38 @@ static void sbi_putc(struct uart_port *port, unsigned char c)
	sbi_console_putchar(c);
}

static void sbi_console_write(struct console *con,
			      const char *s, unsigned n)
static void sbi_0_1_console_write(struct console *con,
				  const char *s, unsigned int n)
{
	struct earlycon_device *dev = con->data;
	uart_console_write(&dev->port, s, n, sbi_putc);
}

static void sbi_dbcn_console_write(struct console *con,
				   const char *s, unsigned int n)
{
	int ret;

	while (n) {
		ret = sbi_debug_console_write(s, n);
		if (ret < 0)
			break;

		s += ret;
		n -= ret;
	}
}

static int __init early_sbi_setup(struct earlycon_device *device,
				  const char *opt)
{
	device->con->write = sbi_console_write;
	if (sbi_debug_console_available)
		device->con->write = sbi_dbcn_console_write;
	else if (IS_ENABLED(CONFIG_RISCV_SBI_V01))
		device->con->write = sbi_0_1_console_write;
	else
		return -ENODEV;

	return 0;
}
EARLYCON_DECLARE(sbi, early_sbi_setup);