Commit c79b972e authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'drm-misc-next-2023-11-17' of git://anongit.freedesktop.org/drm/drm-misc into drm-next 

drm-misc-next for 6.8:

UAPI Changes:
  - drm: Introduce CLOSE_FB ioctl
  - drm/dp-mst: Documentation for the PATH property
  - fdinfo: Do not align to a MB if the size is larger than 1MiB
  - virtio-gpu: add explicit virtgpu context debug name

Cross-subsystem Changes:
  - dma-buf: Add dma_fence_timestamp helper

Core Changes:
  - client: Do not acquire module reference
  - edid: split out drm_eld, add SAD helpers
  - format-helper: Cache format conversion buffers
  - sched: Move from a kthread to a workqueue, rename some internal
    functions to make it clearer, implement dynamic job-flow control
  - gpuvm: Provide more features to handle GEM objects
  - tests: Remove slow kunit tests

Driver Changes:
  - ivpu: Update FW API, new debugfs file, a new NOP job submission test
    mode, improve suspend/resume, PM improvements, MMU PT optimizations,
    firmware profiling frequency support, support for uncached buffers,
    switch to gem shmem helpers, replace kthread with threaded
    interrupts
  - panfrost: PM improvements
  - qaic: Allow to run with a single MSI, support host/device time
    synchronization, misc improvements
  - simplefb: Support memory-regions, support power-domains
  - ssd130x: Unitialized variable fixes
  - omapdrm: dma-fence lockdep annotation fix
  - tidss: dma-fence lockdep annotation fix
  - v3d: Support BCM2712 (RaspberryPi5), Support fdinfo and gputop
  - panel:
    - edp: Support AUO B116XTN02, BOE NT116WHM-N21,836X2, NV116WHM-N49
      V8.0, plus a whole bunch of panels used on Mediatek chromebooks.

Note that the one missing s-o-b for 0da611a8 ("dma-buf: add
dma_fence_timestamp helper") has been supplied here, and rebasing the
entire tree with upsetting committers didn't seem worth the trouble:
https://lore.kernel.org/dri-devel/ce94020e-a7d4-4799-b87d-fbea7b14a268@gmail.com/



Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Maxime Ripard <mripard@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/y4awn5vcfy2lr2hpauo7rc4nfpnc6kksr7btmnwaz7zk63pwoi@gwwef5iqpzva
parents 98b1cc82 3b434a34

Documentation/accel/qaic/aic100.rst

+8 −3
Original line number Diff line number Diff line
@@ -36,8 +36,9 @@ AIC100 DID (0xa100). 


AIC100 does not implement FLR (function level reset).



AIC100 implements MSI but does not implement MSI-X. AIC100 requires 17 MSIs to

operate (1 for MHI, 16 for the DMA Bridge).

AIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to

operate (1 for MHI, 16 for the DMA Bridge). Falling back to 1 MSI is possible in

scenarios where reserving 32 MSIs isn't feasible.



As a PCIe device, AIC100 utilizes BARs to provide host interfaces to the device

hardware. AIC100 provides 3, 64-bit BARs.
@@ -220,10 +221,14 @@ of the defined channels, and their uses. 
+----------------+---------+----------+----------------------------------------+

| QAIC_DEBUG     | 18 & 19 | AMSS     | Not used.                              |

+----------------+---------+----------+----------------------------------------+

| QAIC_TIMESYNC  | 20 & 21 | SBL/AMSS | Used to synchronize timestamps in the  |

| QAIC_TIMESYNC  | 20 & 21 | SBL      | Used to synchronize timestamps in the  |

|                |         |          | device side logs with the host time    |

|                |         |          | source.                                |

+----------------+---------+----------+----------------------------------------+

| QAIC_TIMESYNC  | 22 & 23 | AMSS     | Used to periodically synchronize       |

| _PERIODIC      |         |          | timestamps in the device side logs with|

|                |         |          | the host time source.                  |

+----------------+---------+----------+----------------------------------------+



DMA Bridge

==========

Documentation/accel/qaic/qaic.rst

+28 −0
Original line number Diff line number Diff line
@@ -10,6 +10,9 @@ accelerator products. 
Interrupts

==========



IRQ Storm Mitigation

--------------------



While the AIC100 DMA Bridge hardware implements an IRQ storm mitigation

mechanism, it is still possible for an IRQ storm to occur. A storm can happen

if the workload is particularly quick, and the host is responsive. If the host
@@ -35,6 +38,26 @@ generates 100k IRQs per second (per /proc/interrupts) is reduced to roughly 64 
IRQs over 5 minutes while keeping the host system stable, and having the same

workload throughput performance (within run to run noise variation).



Single MSI Mode

---------------



MultiMSI is not well supported on all systems; virtualized ones even less so

(circa 2023). Between hypervisors masking the PCIe MSI capability structure to

large memory requirements for vIOMMUs (required for supporting MultiMSI), it is

useful to be able to fall back to a single MSI when needed.



To support this fallback, we allow the case where only one MSI is able to be

allocated, and share that one MSI between MHI and the DBCs. The device detects

when only one MSI has been configured and directs the interrupts for the DBCs

to the interrupt normally used for MHI. Unfortunately this means that the

interrupt handlers for every DBC and MHI wake up for every interrupt that

arrives; however, the DBC threaded irq handlers only are started when work to be

done is detected (MHI will always start its threaded handler).



If the DBC is configured to force MSI interrupts, this can circumvent the

software IRQ storm mitigation mentioned above. Since the MSI is shared it is

never disabled, allowing each new entry to the FIFO to trigger a new interrupt.





Neural Network Control (NNC) Protocol

=====================================
@@ -178,3 +201,8 @@ overrides this for that call. Default is 5000 (5 seconds). 


Sets the polling interval in microseconds (us) when datapath polling is active.

Takes effect at the next polling interval. Default is 100 (100 us).



**timesync_delay_ms (unsigned int)**



Sets the time interval in milliseconds (ms) between two consecutive timesync

operations. Default is 1000 (1000 ms).

Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ properties: 
  compatible:

    enum:

      - brcm,2711-v3d

      - brcm,2712-v3d

      - brcm,7268-v3d

      - brcm,7278-v3d

Documentation/gpu/drm-kms-helpers.rst

+6 −0
Original line number Diff line number Diff line
@@ -363,6 +363,12 @@ EDID Helper Functions Reference 
.. kernel-doc:: drivers/gpu/drm/drm_edid.c

   :export:



.. kernel-doc:: include/drm/drm_eld.h

   :internal:



.. kernel-doc:: drivers/gpu/drm/drm_eld.c

   :export:



SCDC Helper Functions Reference

===============================

Documentation/gpu/drm-mm.rst

+6 −0
Original line number Diff line number Diff line
@@ -552,6 +552,12 @@ Overview 
.. kernel-doc:: drivers/gpu/drm/scheduler/sched_main.c

   :doc: Overview



Flow Control

------------



.. kernel-doc:: drivers/gpu/drm/scheduler/sched_main.c

   :doc: Flow Control



Scheduler Function References

-----------------------------