Commit c7b33856 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Drop some unnecessary guards 



Some of the CONFIG_DRM_AMD_DC_FP was added in some non-related FPU code,
which may cause confusion. This commit dropped some of the unnecessary
guards.

Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c84dff70

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+0 −2
Original line number Diff line number Diff line
@@ -707,9 +707,7 @@ void rn_clk_mgr_construct( 
	int is_green_sardine = 0;

	struct clk_log_info log_info = {0};



#if defined(CONFIG_DRM_AMD_DC_FP)

	is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);

#endif



	clk_mgr->base.ctx = ctx;

	clk_mgr->base.funcs = &dcn21_funcs;

drivers/gpu/drm/amd/display/dc/dc.h

+0 −2
Original line number Diff line number Diff line
@@ -2222,11 +2222,9 @@ struct dc_sink_dsc_caps { 
	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),

	// 'false' if they are sink's DSC caps

	bool is_virtual_dpcd_dsc;

#if defined(CONFIG_DRM_AMD_DC_FP)

	// 'true' if MST topology supports DSC passthrough for sink

	// 'false' if MST topology does not support DSC passthrough

	bool is_dsc_passthrough_supported;

#endif

	struct dsc_dec_dpcd_caps dsc_dec_caps;

};

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

+0 −2
Original line number Diff line number Diff line
@@ -827,9 +827,7 @@ struct dc_dsc_config { 
	uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */

	bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */

	int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */

#if defined(CONFIG_DRM_AMD_DC_FP)

	bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */

#endif

	bool is_dp; /* indicate if DSC is applied based on DP's capability */

	uint32_t mst_pbn; /* pbn of display on dsc mst hub */

	const struct dc_dsc_rc_params_override *rc_params_ovrd; /* DM owned memory. If not NULL, apply custom dsc rc params */

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

+0 −2
Original line number Diff line number Diff line
@@ -98,10 +98,8 @@ static void enable_memory_low_power(struct dc *dc) 
		for (i = 0; i < dc->res_pool->stream_enc_count; i++)

			if (dc->res_pool->stream_enc[i]->vpg)

				dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);

#if defined(CONFIG_DRM_AMD_DC_FP)

		for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)

			dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);

#endif

	}



}

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

+0 −2
Original line number Diff line number Diff line
@@ -155,7 +155,6 @@ struct hwseq_private_funcs { 
	void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);

	void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx,

			       struct dc_state *context);

#ifdef CONFIG_DRM_AMD_DC_FP

	void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);

	void (*update_force_pstate)(struct dc *dc, struct dc_state *context);

	void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
@@ -170,7 +169,6 @@ struct hwseq_private_funcs { 
			struct dc_state *context,

			struct dc *dc);

	bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);

#endif

	void (*reset_back_end_for_pipe)(struct dc *dc,

			struct pipe_ctx *pipe_ctx,

			struct dc_state *context);