Commit c7c0d13d authored by Chao-ying Fu's avatar Chao-ying Fu Committed by Thomas Gleixner
Browse files

irqchip/mips-gic: Setup defaults in each cluster 



In multi-cluster MIPS I6500 systems, there is a GIC per cluster.

The default shared interrupt setup configured in gic_of_init() applies only
to the GIC in the cluster containing the boot CPU, leaving the GICs of
other clusters unconfigured.

Configure the other clusters as well.

Signed-off-by: default avatarChao-ying Fu <cfu@wavecomp.com>
Signed-off-by: default avatarDragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: default avatarAleksandar Rikalo <arikalo@gmail.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Tested-by: default avatarSerge Semin <fancer.lancer@gmail.com>
Tested-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lore.kernel.org/all/20241028175935.51250-4-arikalo@gmail.com
parent d9e2ed61

drivers/irqchip/irq-mips-gic.c

+24 −6
Original line number Diff line number Diff line
@@ -764,7 +764,7 @@ static int gic_cpu_startup(unsigned int cpu) 
static int __init gic_of_init(struct device_node *node,

			      struct device_node *parent)

{

	unsigned int cpu_vec, i, gicconfig;

	unsigned int cpu_vec, i, gicconfig, cl, nclusters;

	unsigned long reserved;

	phys_addr_t gic_base;

	struct resource res;
@@ -845,12 +845,30 @@ static int __init gic_of_init(struct device_node *node, 


	board_bind_eic_interrupt = &gic_bind_eic_interrupt;



	/* Setup defaults */

	/*

	 * Initialise each cluster's GIC shared registers to sane default

	 * values.

	 * Otherwise, the IPI set up will be erased if we move code

	 * to gic_cpu_startup for each cpu.

	 */

	nclusters = mips_cps_numclusters();

	for (cl = 0; cl < nclusters; cl++) {

		if (cl == cpu_cluster(&current_cpu_data)) {

			for (i = 0; i < gic_shared_intrs; i++) {

				change_gic_pol(i, GIC_POL_ACTIVE_HIGH);

				change_gic_trig(i, GIC_TRIG_LEVEL);

				write_gic_rmask(i);

			}

		} else {

			mips_cm_lock_other(cl, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);

			for (i = 0; i < gic_shared_intrs; i++) {

				change_gic_redir_pol(i, GIC_POL_ACTIVE_HIGH);

				change_gic_redir_trig(i, GIC_TRIG_LEVEL);

				write_gic_redir_rmask(i);

			}

			mips_cm_unlock_other();

		}

	}



	return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,

				 "irqchip/mips/gic:starting",