Commit c7c7eb4f authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/sysregs' into for-next/core 

* for-next/sysregs:
  arm64/sysreg: Update TCR_EL1 register
  arm64: sysreg: Add validation checks to sysreg header generation script
  arm64: sysreg: Correct sign definitions for EIESB and DoubleLock
  arm64: sysreg: Fix and tidy up sysreg field definitions
parents 712f4ee7 14f15855

arch/arm64/include/asm/sysreg.h

+0 −2
Original line number Diff line number Diff line
@@ -281,8 +281,6 @@ 
#define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)

#define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)



#define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)



#define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)

#define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)

#define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)

arch/arm64/tools/gen-sysreg.awk

+20 −0
Original line number Diff line number Diff line
@@ -122,6 +122,10 @@ $1 == "SysregFields" && block_current() == "Root" { 
	res1 = "UL(0)"

	unkn = "UL(0)"



	if (reg in defined_fields)

		fatal("Duplicate SysregFields definition for " reg)

	defined_fields[reg] = 1



	next_bit = 63



	next
@@ -162,6 +166,10 @@ $1 == "Sysreg" && block_current() == "Root" { 
	res1 = "UL(0)"

	unkn = "UL(0)"



	if (reg in defined_regs)

		fatal("Duplicate Sysreg definition for " reg)

	defined_regs[reg] = 1



	define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2)

	define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")")
@@ -284,6 +292,8 @@ $1 == "SignedEnum" && (block_current() == "Sysreg" || block_current() == "Sysreg 
	define_field(reg, field, msb, lsb)

	define_field_sign(reg, field, "true")



	delete seen_enum_vals



	next

}
@@ -297,6 +307,8 @@ $1 == "UnsignedEnum" && (block_current() == "Sysreg" || block_current() == "Sysr 
	define_field(reg, field, msb, lsb)

	define_field_sign(reg, field, "false")



	delete seen_enum_vals



	next

}
@@ -309,6 +321,8 @@ $1 == "Enum" && (block_current() == "Sysreg" || block_current() == "SysregFields 


	define_field(reg, field, msb, lsb)



	delete seen_enum_vals



	next

}
@@ -320,6 +334,8 @@ $1 == "EndEnum" && block_current() == "Enum" { 
	lsb = null

	print ""



	delete seen_enum_vals



	block_pop()

	next

}
@@ -329,6 +345,10 @@ $1 == "EndEnum" && block_current() == "Enum" { 
	val = $1

	name = $2



	if (val in seen_enum_vals)

		fatal("Duplicate Enum value " val " for " name)

	seen_enum_vals[val] = 1



	define(reg "_" field "_" name, "UL(" val ")")

	next

}

arch/arm64/tools/sysreg

+49 −21
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
# Mapping	<name_EL1>

# EndSysreg



# Where multiple system regsiters are not VHE aliases but share a

# Where multiple system registers are not VHE aliases but share a

# common layout, a SysregFields block can be used to describe the

# shared layout:
@@ -54,7 +54,7 @@ 
#

# In general it is recommended that new enumeration items be named for the

# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration

# item ACCDATA) though it may be more taseful to do something else.

# item ACCDATA) though it may be more tasteful to do something else.



Sysreg	OSDTRRX_EL1	2	0	0	0	2

Res0	63:32
@@ -474,7 +474,7 @@ EndEnum 
Enum	7:4	Security

	0b0000	NI

	0b0001	EL3

	0b0001	NSACR_RFR

	0b0010	NSACR_RFR

EndEnum

UnsignedEnum	3:0	ProgMod

	0b0000	NI
@@ -1693,7 +1693,7 @@ UnsignedEnum 43:40 TraceFilt 
	0b0000	NI

	0b0001	IMP

EndEnum

UnsignedEnum	39:36	DoubleLock

SignedEnum	39:36	DoubleLock

	0b0000	IMP

	0b1111	NI

EndEnum
@@ -2409,7 +2409,7 @@ UnsignedEnum 11:8 ASID2 
	0b0000	NI

	0b0001	IMP

EndEnum

SignedEnum	7:4	EIESB

UnsignedEnum	7:4	EIESB

	0b0000	NI

	0b0001	ToEL3

	0b0010	ToELx
@@ -2528,10 +2528,6 @@ Field 17:16 ZEN 
Res0	15:0

EndSysreg



Sysreg	CPACR_EL12      3	5	1	0	2

Mapping	CPACR_EL1

EndSysreg



Sysreg	CPACRALIAS_EL1  3	0	1	4	4

Mapping	CPACR_EL1

EndSysreg
@@ -2576,10 +2572,6 @@ Sysreg PFAR_EL12 3 5 6 0 5 
Mapping	PFAR_EL1

EndSysreg



Sysreg	RCWSMASK_EL1	3	0	13	0	3

Field	63:0	RCWSMASK

EndSysreg



Sysreg	SCTLR2_EL1      3	0	1	0	3

Res0    63:13

Field   12      CPTM0
@@ -4765,17 +4757,53 @@ Field 37 TBI0 
Field   36      AS

Res0    35

Field   34:32   IPS

Field   31:30   TG1

Field   29:28   SH1

Field   27:26   ORGN1

Field   25:24   IRGN1

Enum	31:30   TG1

	0b01	16K

	0b10	4K

	0b11	64K

EndEnum

Enum	29:28   SH1

	0b00	NONE

	0b10	OUTER

	0b11	INNER

EndEnum

Enum	27:26  ORGN1

	0b00	NC

	0b01	WBWA

	0b10	WT

	0b11	WBnWA

EndEnum

Enum	25:24   IRGN1

	0b00	NC

	0b01	WBWA

	0b10	WT

	0b11	WBnWA

EndEnum

Field   23      EPD1

Field   22      A1

Field   21:16   T1SZ

Field   15:14   TG0

Field   13:12   SH0

Field   11:10   ORGN0

Field   9:8     IRGN0

Enum	15:14   TG0

	0b00	4K

	0b01	64K

	0b10	16K

EndEnum

Enum	13:12   SH0

	0b00	NONE

	0b10	OUTER

	0b11	INNER

EndEnum

Enum	11:10  ORGN0

	0b00	NC

	0b01	WBWA

	0b10	WT

	0b11	WBnWA

EndEnum

Enum	9:8   IRGN0

	0b00	NC

	0b01	WBWA

	0b10	WT

	0b11	WBnWA

EndEnum

Field   7       EPD0

Res0    6

Field   5:0     T0SZ