Commit c81dbc49 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-xe-fixes-2025-05-15-1' of... 

Merge tag 'drm-xe-fixes-2025-05-15-1' of https://gitlab.freedesktop.org/drm/xe/kernel

 into drm-fixes

Core Changes:
- Add timeslicing and allocation restriction for SVM

Driver Changes:
- Fix shrinker debugfs name
- Add HW workaround to Xe2
- Fix SVM when mixing GPU and CPU atomics
- Fix per client engine utilization due to active contexts
  not saving timestamp with lite restore enabled.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/qil4scyn6ucnt43u5ju64bi7r7n5r36k4pz5rsh2maz7isle6g@lac3jpsjrrvs
parents f7bf6bdb 617d824c

drivers/gpu/drm/drm_gpusvm.c

+32 −5
Original line number Diff line number Diff line
@@ -1118,6 +1118,10 @@ static void __drm_gpusvm_range_unmap_pages(struct drm_gpusvm *gpusvm, 
	lockdep_assert_held(&gpusvm->notifier_lock);



	if (range->flags.has_dma_mapping) {

		struct drm_gpusvm_range_flags flags = {

			.__flags = range->flags.__flags,

		};



		for (i = 0, j = 0; i < npages; j++) {

			struct drm_pagemap_device_addr *addr = &range->dma_addr[j];
@@ -1131,8 +1135,12 @@ static void __drm_gpusvm_range_unmap_pages(struct drm_gpusvm *gpusvm, 
							    dev, *addr);

			i += 1 << addr->order;

		}

		range->flags.has_devmem_pages = false;

		range->flags.has_dma_mapping = false;



		/* WRITE_ONCE pairs with READ_ONCE for opportunistic checks */

		flags.has_devmem_pages = false;

		flags.has_dma_mapping = false;

		WRITE_ONCE(range->flags.__flags, flags.__flags);



		range->dpagemap = NULL;

	}

}
@@ -1334,6 +1342,7 @@ int drm_gpusvm_range_get_pages(struct drm_gpusvm *gpusvm, 
	int err = 0;

	struct dev_pagemap *pagemap;

	struct drm_pagemap *dpagemap;

	struct drm_gpusvm_range_flags flags;



retry:

	hmm_range.notifier_seq = mmu_interval_read_begin(notifier);
@@ -1378,7 +1387,8 @@ int drm_gpusvm_range_get_pages(struct drm_gpusvm *gpusvm, 
	 */

	drm_gpusvm_notifier_lock(gpusvm);



	if (range->flags.unmapped) {

	flags.__flags = range->flags.__flags;

	if (flags.unmapped) {

		drm_gpusvm_notifier_unlock(gpusvm);

		err = -EFAULT;

		goto err_free;
@@ -1454,6 +1464,11 @@ int drm_gpusvm_range_get_pages(struct drm_gpusvm *gpusvm, 
				goto err_unmap;

			}



			if (ctx->devmem_only) {

				err = -EFAULT;

				goto err_unmap;

			}



			addr = dma_map_page(gpusvm->drm->dev,

					    page, 0,

					    PAGE_SIZE << order,
@@ -1469,14 +1484,17 @@ int drm_gpusvm_range_get_pages(struct drm_gpusvm *gpusvm, 
		}

		i += 1 << order;

		num_dma_mapped = i;

		range->flags.has_dma_mapping = true;

		flags.has_dma_mapping = true;

	}



	if (zdd) {

		range->flags.has_devmem_pages = true;

		flags.has_devmem_pages = true;

		range->dpagemap = dpagemap;

	}



	/* WRITE_ONCE pairs with READ_ONCE for opportunistic checks */

	WRITE_ONCE(range->flags.__flags, flags.__flags);



	drm_gpusvm_notifier_unlock(gpusvm);

	kvfree(pfns);

set_seqno:
@@ -1765,6 +1783,8 @@ int drm_gpusvm_migrate_to_devmem(struct drm_gpusvm *gpusvm, 
		goto err_finalize;



	/* Upon success bind devmem allocation to range and zdd */

	devmem_allocation->timeslice_expiration = get_jiffies_64() +

		msecs_to_jiffies(ctx->timeslice_ms);

	zdd->devmem_allocation = devmem_allocation;	/* Owns ref */



err_finalize:
@@ -1985,6 +2005,13 @@ static int __drm_gpusvm_migrate_to_ram(struct vm_area_struct *vas, 
	void *buf;

	int i, err = 0;



	if (page) {

		zdd = page->zone_device_data;

		if (time_before64(get_jiffies_64(),

				  zdd->devmem_allocation->timeslice_expiration))

			return 0;

	}



	start = ALIGN_DOWN(fault_addr, size);

	end = ALIGN(fault_addr + 1, size);

drivers/gpu/drm/xe/instructions/xe_mi_commands.h

+4 −0
Original line number Diff line number Diff line
@@ -47,6 +47,10 @@ 
#define   MI_LRI_FORCE_POSTED		REG_BIT(12)

#define   MI_LRI_LEN(x)			(((x) & 0xff) + 1)



#define MI_STORE_REGISTER_MEM		(__MI_INSTR(0x24) | XE_INSTR_NUM_DW(4))

#define   MI_SRM_USE_GGTT		REG_BIT(22)

#define   MI_SRM_ADD_CS_OFFSET		REG_BIT(19)



#define MI_FLUSH_DW			__MI_INSTR(0x26)

#define   MI_FLUSH_DW_PROTECTED_MEM_EN	REG_BIT(22)

#define   MI_FLUSH_DW_STORE_INDEX	REG_BIT(21)

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+5 −0
Original line number Diff line number Diff line
@@ -43,6 +43,10 @@ 
#define XEHPC_BCS8_RING_BASE			0x3ee000

#define GSCCS_RING_BASE				0x11a000



#define ENGINE_ID(base)				XE_REG((base) + 0x8c)

#define   ENGINE_INSTANCE_ID			REG_GENMASK(9, 4)

#define   ENGINE_CLASS_ID			REG_GENMASK(2, 0)



#define RING_TAIL(base)				XE_REG((base) + 0x30)

#define   TAIL_ADDR				REG_GENMASK(20, 3)
@@ -154,6 +158,7 @@ 
#define   STOP_RING				REG_BIT(8)



#define RING_CTX_TIMESTAMP(base)		XE_REG((base) + 0x3a8)

#define RING_CTX_TIMESTAMP_UDW(base)		XE_REG((base) + 0x3ac)

#define CSBE_DEBUG_STATUS(base)			XE_REG((base) + 0x3fc)



#define RING_FORCE_TO_NONPRIV(base, i)		XE_REG(((base) + 0x4d0) + (i) * 4)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -157,6 +157,7 @@ 
#define XEHPG_SC_INSTDONE_EXTRA2		XE_REG_MCR(0x7108)



#define COMMON_SLICE_CHICKEN4			XE_REG(0x7300, XE_REG_OPTION_MASKED)

#define   SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE	REG_BIT(12)

#define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)



#define COMMON_SLICE_CHICKEN3				XE_REG(0x7304, XE_REG_OPTION_MASKED)

drivers/gpu/drm/xe/regs/xe_lrc_layout.h

+2 −0
Original line number Diff line number Diff line
@@ -11,7 +11,9 @@ 
#define CTX_RING_TAIL			(0x06 + 1)

#define CTX_RING_START			(0x08 + 1)

#define CTX_RING_CTL			(0x0a + 1)

#define CTX_BB_PER_CTX_PTR		(0x12 + 1)

#define CTX_TIMESTAMP			(0x22 + 1)

#define CTX_TIMESTAMP_UDW		(0x24 + 1)

#define CTX_INDIRECT_RING_STATE		(0x26 + 1)

#define CTX_PDP0_UDW			(0x30 + 1)

#define CTX_PDP0_LDW			(0x32 + 1)