Unverified Commit c85688e2 authored by Eric Chan's avatar Eric Chan Committed by Palmer Dabbelt
Browse files

riscv/barrier: Consolidate fence definitions 



Disparate fence implementations are consolidated into fence.h.
Also introduce RISCV_FENCE_ASM to make fence macro more reusable.

Signed-off-by: default avatarEric Chan <ericchancf@google.com>
Reviewed-by: default avatarAndrea Parri <parri.andrea@gmail.com>
Reviewed-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Tested-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20240217131316.3668927-1-ericchancf@google.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent b3c8064c

arch/riscv/include/asm/atomic.h

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@@ -17,7 +17,6 @@ 
#endif



#include <asm/cmpxchg.h>

#include <asm/barrier.h>



#define __atomic_acquire_fence()					\

	__asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory")

arch/riscv/include/asm/barrier.h

+1 −2
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@@ -11,13 +11,12 @@ 
#define _ASM_RISCV_BARRIER_H



#ifndef __ASSEMBLY__

#include <asm/fence.h>



#define nop()		__asm__ __volatile__ ("nop")

#define __nops(n)	".rept	" #n "\nnop\n.endr\n"

#define nops(n)		__asm__ __volatile__ (__nops(n))



#define RISCV_FENCE(p, s) \

	__asm__ __volatile__ ("fence " #p "," #s : : : "memory")



/* These barriers need to enforce ordering on both devices or memory. */

#define __mb()		RISCV_FENCE(iorw, iorw)

arch/riscv/include/asm/cmpxchg.h

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@@ -8,7 +8,6 @@ 


#include <linux/bug.h>



#include <asm/barrier.h>

#include <asm/fence.h>



#define __xchg_relaxed(ptr, new, size)					\

arch/riscv/include/asm/fence.h

+7 −3
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#ifndef _ASM_RISCV_FENCE_H

#define _ASM_RISCV_FENCE_H



#define RISCV_FENCE_ASM(p, s)		"\tfence " #p "," #s "\n"

#define RISCV_FENCE(p, s) \

	({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); })



#ifdef CONFIG_SMP

#define RISCV_ACQUIRE_BARRIER		"\tfence r , rw\n"

#define RISCV_RELEASE_BARRIER		"\tfence rw,  w\n"

#define RISCV_FULL_BARRIER		"\tfence rw, rw\n"

#define RISCV_ACQUIRE_BARRIER		RISCV_FENCE_ASM(r, rw)

#define RISCV_RELEASE_BARRIER		RISCV_FENCE_ASM(rw, w)

#define RISCV_FULL_BARRIER		RISCV_FENCE_ASM(rw, rw)

#else

#define RISCV_ACQUIRE_BARRIER

#define RISCV_RELEASE_BARRIER

arch/riscv/include/asm/io.h

+4 −4
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@@ -47,10 +47,10 @@ 
 * sufficient to ensure this works sanely on controllers that support I/O

 * writes.

 */

#define __io_pbr()	__asm__ __volatile__ ("fence io,i"  : : : "memory");

#define __io_par(v)	__asm__ __volatile__ ("fence i,ior" : : : "memory");

#define __io_pbw()	__asm__ __volatile__ ("fence iow,o" : : : "memory");

#define __io_paw()	__asm__ __volatile__ ("fence o,io"  : : : "memory");

#define __io_pbr()	RISCV_FENCE(io, i)

#define __io_par(v)	RISCV_FENCE(i, ior)

#define __io_pbw()	RISCV_FENCE(iow, o)

#define __io_paw()	RISCV_FENCE(o, io)



/*

 * Accesses from a single hart to a single I/O address must be ordered.  This