Commit c8a07478 authored by Nitin Rawat's avatar Nitin Rawat Committed by Bjorn Andersson
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arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 soc 



Add UFS host controller and PHY nodes for sc7280 soc.

Signed-off-by: default avatarNitin Rawat <quic_nitirawa@quicinc.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
[luca: various cleanups and additions as written in the cover letter]
Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Acked-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20231205-sc7280-ufs-v6-2-ad6ca7796de7@fairphone.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 990b6c92

arch/arm64/boot/dts/qcom/sc7280.dtsi

+72 −1
Original line number Diff line number Diff line
@@ -912,7 +912,7 @@ gcc: clock-controller@100000 { 
			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,

				 <0>, <&pcie1_phy>,

				 <0>, <0>, <0>,

				 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,

				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;

			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",

				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
@@ -2244,6 +2244,77 @@ pcie1_phy: phy@1c0e000 { 
			status = "disabled";

		};



		ufs_mem_hc: ufs@1d84000 {

			compatible = "qcom,sc7280-ufshc", "qcom,ufshc",

				     "jedec,ufs-2.0";

			reg = <0x0 0x01d84000 0x0 0x3000>;

			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

			phys = <&ufs_mem_phy>;

			phy-names = "ufsphy";

			lanes-per-direction = <2>;

			#reset-cells = <1>;

			resets = <&gcc GCC_UFS_PHY_BCR>;

			reset-names = "rst";



			power-domains = <&gcc GCC_UFS_PHY_GDSC>;

			required-opps = <&rpmhpd_opp_nom>;



			iommus = <&apps_smmu 0x80 0x0>;

			dma-coherent;



			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

					 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;

			interconnect-names = "ufs-ddr", "cpu-ufs";



			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

				 <&gcc GCC_UFS_PHY_AHB_CLK>,

				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

			clock-names = "core_clk",

				      "bus_aggr_clk",

				      "iface_clk",

				      "core_clk_unipro",

				      "ref_clk",

				      "tx_lane0_sync_clk",

				      "rx_lane0_sync_clk",

				      "rx_lane1_sync_clk";

			freq-table-hz =

				<75000000 300000000>,

				<0 0>,

				<0 0>,

				<75000000 300000000>,

				<0 0>,

				<0 0>,

				<0 0>,

				<0 0>;

			status = "disabled";

		};



		ufs_mem_phy: phy@1d87000 {

			compatible = "qcom,sc7280-qmp-ufs-phy";

			reg = <0x0 0x01d87000 0x0 0xe00>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,

				 <&gcc GCC_UFS_1_CLKREF_EN>;

			clock-names = "ref", "ref_aux", "qref";



			power-domains = <&rpmhpd SC7280_MX>;



			resets = <&ufs_mem_hc 0>;

			reset-names = "ufsphy";



			#clock-cells = <1>;

			#phy-cells = <0>;



			status = "disabled";

		};



		ipa: ipa@1e40000 {

			compatible = "qcom,sc7280-ipa";