Commit c8bd9bd6 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP 



The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB)
that generates the RTC clock. Add clock, reset and power domain support
for it.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240614071932.1014067-2-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent d6c5fc9a

drivers/clk/renesas/r9a08g045-cpg.c

+6 −0
Original line number Diff line number Diff line
@@ -215,6 +215,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { 
	DEF_MOD("eth1_refclk",		R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),

	DEF_MOD("scif0_clk_pck",	R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),

	DEF_MOD("gpio_hclk",		R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),

	DEF_MOD("vbat_bclk",		R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),

};



static const struct rzg2l_reset r9a08g045_resets[] = {
@@ -231,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { 
	DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),

	DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),

	DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),

	DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),

};



static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
@@ -238,6 +240,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { 
	MOD_CLK_BASE + R9A08G045_IA55_PCLK,

	MOD_CLK_BASE + R9A08G045_IA55_CLK,

	MOD_CLK_BASE + R9A08G045_DMAC_ACLK,

	MOD_CLK_BASE + R9A08G045_VBAT_BCLK,

};



static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
@@ -275,6 +278,9 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { 
	DEF_PD("scif0",		R9A08G045_PD_SCIF0,

				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),

				RZG2L_PD_F_NONE),

	DEF_PD("vbat",		R9A08G045_PD_VBAT,

				DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),

				RZG2L_PD_F_ALWAYS_ON),

};



const struct rzg2l_cpg_info r9a08g045_cpg_info = {