Commit c8d2d76d authored by Andy Tang's avatar Andy Tang Committed by Ulf Hansson
Browse files

mmc: sdhci-of-esdhc: limit the SDHC clock frequency 



The highest clock frequency for eMMC HS200 mode on ls1043a
is 116.7Mhz according to its specification.
So add the limit to gate the frequency.

Signed-off-by: default avatarAndy Tang <andy.tang@nxp.com>
Link: https://lore.kernel.org/r/20221202075905.25363-1-andy.tang@nxp.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 496182a3

drivers/mmc/host/sdhci-of-esdhc.c

+7 −0
Original line number Diff line number Diff line
@@ -42,6 +42,12 @@ static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 
	.max_clk[MMC_TIMING_SD_HS] = 46500000,

};



static const struct esdhc_clk_fixup ls1043a_esdhc_clk = {

	.sd_dflt_max_clk = 25000000,

	.max_clk[MMC_TIMING_UHS_SDR104] = 116700000,

	.max_clk[MMC_TIMING_MMC_HS200] = 116700000,

};



static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {

	.sd_dflt_max_clk = 25000000,

	.max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
@@ -63,6 +69,7 @@ static const struct esdhc_clk_fixup p1010_esdhc_clk = { 


static const struct of_device_id sdhci_esdhc_of_match[] = {

	{ .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},

	{ .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk},

	{ .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},

	{ .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},

	{ .compatible = "fsl,p1010-esdhc",   .data = &p1010_esdhc_clk},