Commit c99b2e8c authored by Dave Jiang's avatar Dave Jiang Committed by Dan Williams
Browse files

cxl: update names for interleave ways conversion macros



Change names for interleave ways macros to clearly indicate which
variable is encoded and which is the actual ways value.

ways == interleave ways
eiw == encoded interleave ways

Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/167027516228.3124679.11265039496968588580.stgit@djiang5-desk3.ch.intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 83351ddb
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+3 −3
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
	}
	/* IW: 3,6,12 add a modulo calculation to 'n' */
	if (!is_power_of_2(iw)) {
		if (ways_to_cxl(iw, &eiw))
		if (ways_to_eiw(iw, &eiw))
			return -1;
		hpa &= GENMASK_ULL(51, eiw + ig);
		n |= do_div(hpa, 3) << i;
@@ -161,7 +161,7 @@ static int cxl_acpi_cfmws_verify(struct device *dev,
		return -EINVAL;
	}

	rc = cxl_to_ways(cfmws->interleave_ways, &ways);
	rc = eiw_to_ways(cfmws->interleave_ways, &ways);
	if (rc) {
		dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
			cfmws->interleave_ways);
@@ -221,7 +221,7 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
		return 0;
	}

	rc = cxl_to_ways(cfmws->interleave_ways, &ways);
	rc = eiw_to_ways(cfmws->interleave_ways, &ways);
	if (rc)
		return rc;
	rc = eig_to_granularity(cfmws->granularity, &ig);
+3 −3
Original line number Diff line number Diff line
@@ -494,7 +494,7 @@ static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl)
	 * Input validation ensures these warns never fire, but otherwise
	 * suppress unititalized variable usage warnings.
	 */
	if (WARN_ONCE(ways_to_cxl(cxld->interleave_ways, &eiw),
	if (WARN_ONCE(ways_to_eiw(cxld->interleave_ways, &eiw),
		      "invalid interleave_ways: %d\n", cxld->interleave_ways))
		return;
	if (WARN_ONCE(granularity_to_eig(cxld->interleave_granularity, &eig),
@@ -741,7 +741,7 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
		}
		cxld->target_type = CXL_DECODER_EXPANDER;
	}
	rc = cxl_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),
	rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),
			  &cxld->interleave_ways);
	if (rc) {
		dev_warn(&port->dev,
+3 −3
Original line number Diff line number Diff line
@@ -324,7 +324,7 @@ static ssize_t interleave_ways_store(struct device *dev,
	if (rc)
		return rc;

	rc = ways_to_cxl(val, &iw);
	rc = ways_to_eiw(val, &iw);
	if (rc)
		return rc;

@@ -1036,7 +1036,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
		return rc;
	}

	rc = ways_to_cxl(parent_iw, &peiw);
	rc = ways_to_eiw(parent_iw, &peiw);
	if (rc) {
		dev_dbg(&cxlr->dev, "%s:%s: invalid parent interleave: %d\n",
			dev_name(parent_port->uport),
@@ -1045,7 +1045,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
	}

	iw = cxl_rr->nr_targets;
	rc = ways_to_cxl(iw, &eiw);
	rc = ways_to_eiw(iw, &eiw);
	if (rc) {
		dev_dbg(&cxlr->dev, "%s:%s: invalid port interleave: %d\n",
			dev_name(port->uport), dev_name(&port->dev), iw);
+7 −7
Original line number Diff line number Diff line
@@ -83,14 +83,14 @@ static inline int eig_to_granularity(u16 eig, unsigned int *granularity)
}

/* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
static inline int cxl_to_ways(u8 eniw, unsigned int *val)
static inline int eiw_to_ways(u8 eiw, unsigned int *ways)
{
	switch (eniw) {
	switch (eiw) {
	case 0 ... 4:
		*val = 1 << eniw;
		*ways = 1 << eiw;
		break;
	case 8 ... 10:
		*val = 3 << (eniw - 8);
		*ways = 3 << (eiw - 8);
		break;
	default:
		return -EINVAL;
@@ -108,12 +108,12 @@ static inline int granularity_to_eig(int granularity, u16 *eig)
	return 0;
}

static inline int ways_to_cxl(unsigned int ways, u8 *iw)
static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
{
	if (ways > 16)
		return -EINVAL;
	if (is_power_of_2(ways)) {
		*iw = ilog2(ways);
		*eiw = ilog2(ways);
		return 0;
	}
	if (ways % 3)
@@ -121,7 +121,7 @@ static inline int ways_to_cxl(unsigned int ways, u8 *iw)
	ways /= 3;
	if (!is_power_of_2(ways))
		return -EINVAL;
	*iw = ilog2(ways) + 8;
	*eiw = ilog2(ways) + 8;
	return 0;
}