Commit c9cfed29 authored by Matthew Brost's avatar Matthew Brost Committed by Thomas Hellström
Browse files

drm/xe: Make all GuC ABI shift values unsigned 

All GuC ABI definitions are unsigned and not defining as unsigned is
causing build errors [1].

[1] https://lore.kernel.org/all/20240123111235.3097079-1-geert@linux-m68k.org/



Fixes: dd08ebf6 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: default avatarMatthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarThomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240131025424.2087936-1-matthew.brost@intel.com


(cherry picked from commit d83d8ae2)
Signed-off-by: default avatarThomas Hellström <thomas.hellstrom@linux.intel.com>
parent ed2bdf3b

drivers/gpu/drm/xe/abi/guc_actions_abi.h

+2 −2
Original line number Diff line number Diff line
@@ -50,8 +50,8 @@ 


#define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0

#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY		(0xffff << 16)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN		(0xffff << 0)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY		(0xffffu << 16)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN		(0xffffu << 0)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32		GUC_HXG_REQUEST_MSG_n_DATAn

#define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64		GUC_HXG_REQUEST_MSG_n_DATAn

drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h

+2 −2
Original line number Diff line number Diff line
@@ -242,8 +242,8 @@ struct slpc_shared_data { 
		(HOST2GUC_PC_SLPC_REQUEST_REQUEST_MSG_MIN_LEN + \

			HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS)

#define HOST2GUC_PC_SLPC_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0

#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID		(0xff << 8)

#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC	(0xff << 0)

#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID		(0xffu << 8)

#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC	(0xffu << 0)

#define HOST2GUC_PC_SLPC_REQUEST_MSG_N_EVENT_DATA_N	GUC_HXG_REQUEST_MSG_n_DATAn



#endif

drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h

+4 −4
Original line number Diff line number Diff line
@@ -82,11 +82,11 @@ static_assert(sizeof(struct guc_ct_buffer_desc) == 64); 
#define GUC_CTB_HDR_LEN				1u

#define GUC_CTB_MSG_MIN_LEN			GUC_CTB_HDR_LEN

#define GUC_CTB_MSG_MAX_LEN			256u

#define GUC_CTB_MSG_0_FENCE			(0xffff << 16)

#define GUC_CTB_MSG_0_FORMAT			(0xf << 12)

#define GUC_CTB_MSG_0_FENCE			(0xffffu << 16)

#define GUC_CTB_MSG_0_FORMAT			(0xfu << 12)

#define   GUC_CTB_FORMAT_HXG			0u

#define GUC_CTB_MSG_0_RESERVED			(0xf << 8)

#define GUC_CTB_MSG_0_NUM_DWORDS		(0xff << 0)

#define GUC_CTB_MSG_0_RESERVED			(0xfu << 8)

#define GUC_CTB_MSG_0_NUM_DWORDS		(0xffu << 0)



/**

 * DOC: CTB HXG Message

drivers/gpu/drm/xe/abi/guc_klvs_abi.h

+3 −3
Original line number Diff line number Diff line
@@ -31,9 +31,9 @@ 
 */



#define GUC_KLV_LEN_MIN				1u

#define GUC_KLV_0_KEY				(0xffff << 16)

#define GUC_KLV_0_LEN				(0xffff << 0)

#define GUC_KLV_n_VALUE				(0xffffffff << 0)

#define GUC_KLV_0_KEY				(0xffffu << 16)

#define GUC_KLV_0_LEN				(0xffffu << 0)

#define GUC_KLV_n_VALUE				(0xffffffffu << 0)



/**

 * DOC: GuC Self Config KLVs

drivers/gpu/drm/xe/abi/guc_messages_abi.h

+10 −10
Original line number Diff line number Diff line
@@ -40,18 +40,18 @@ 
 */



#define GUC_HXG_MSG_MIN_LEN			1u

#define GUC_HXG_MSG_0_ORIGIN			(0x1 << 31)

#define GUC_HXG_MSG_0_ORIGIN			(0x1u << 31)

#define   GUC_HXG_ORIGIN_HOST			0u

#define   GUC_HXG_ORIGIN_GUC			1u

#define GUC_HXG_MSG_0_TYPE			(0x7 << 28)

#define GUC_HXG_MSG_0_TYPE			(0x7u << 28)

#define   GUC_HXG_TYPE_REQUEST			0u

#define   GUC_HXG_TYPE_EVENT			1u

#define   GUC_HXG_TYPE_NO_RESPONSE_BUSY		3u

#define   GUC_HXG_TYPE_NO_RESPONSE_RETRY	5u

#define   GUC_HXG_TYPE_RESPONSE_FAILURE		6u

#define   GUC_HXG_TYPE_RESPONSE_SUCCESS		7u

#define GUC_HXG_MSG_0_AUX			(0xfffffff << 0)

#define GUC_HXG_MSG_n_PAYLOAD			(0xffffffff << 0)

#define GUC_HXG_MSG_0_AUX			(0xfffffffu << 0)

#define GUC_HXG_MSG_n_PAYLOAD			(0xffffffffu << 0)



/**

 * DOC: HXG Request
@@ -85,8 +85,8 @@ 
 */



#define GUC_HXG_REQUEST_MSG_MIN_LEN		GUC_HXG_MSG_MIN_LEN

#define GUC_HXG_REQUEST_MSG_0_DATA0		(0xfff << 16)

#define GUC_HXG_REQUEST_MSG_0_ACTION		(0xffff << 0)

#define GUC_HXG_REQUEST_MSG_0_DATA0		(0xfffu << 16)

#define GUC_HXG_REQUEST_MSG_0_ACTION		(0xffffu << 0)

#define GUC_HXG_REQUEST_MSG_n_DATAn		GUC_HXG_MSG_n_PAYLOAD



/**
@@ -117,8 +117,8 @@ 
 */



#define GUC_HXG_EVENT_MSG_MIN_LEN		GUC_HXG_MSG_MIN_LEN

#define GUC_HXG_EVENT_MSG_0_DATA0		(0xfff << 16)

#define GUC_HXG_EVENT_MSG_0_ACTION		(0xffff << 0)

#define GUC_HXG_EVENT_MSG_0_DATA0		(0xfffu << 16)

#define GUC_HXG_EVENT_MSG_0_ACTION		(0xffffu << 0)

#define GUC_HXG_EVENT_MSG_n_DATAn		GUC_HXG_MSG_n_PAYLOAD



/**
@@ -188,8 +188,8 @@ 
 */



#define GUC_HXG_FAILURE_MSG_LEN			GUC_HXG_MSG_MIN_LEN

#define GUC_HXG_FAILURE_MSG_0_HINT		(0xfff << 16)

#define GUC_HXG_FAILURE_MSG_0_ERROR		(0xffff << 0)

#define GUC_HXG_FAILURE_MSG_0_HINT		(0xfffu << 16)

#define GUC_HXG_FAILURE_MSG_0_ERROR		(0xffffu << 0)



/**

 * DOC: HXG Response