Commit c9e3878a authored by Timur Tabi's avatar Timur Tabi Committed by Danilo Krummrich
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Revert "drm/nouveau/gsp: add support for GA100"



This reverts commit 20e0c197.

Despite claiming to add GA100 support, that commit actually has quite
a few problems.  It falsely claims that there is no VBIOS.  GA100 does
have a VBIOS, but it has no display engine, so it cannot use the
PRAMIN method the read VBIOS and must fall back to using PROM.

For whatever reason, the VBIOS on GA100 has an "Init-from-ROM"
(IFR) header where the PCI Expansion ROM would normally be found.
So to find that ROM, Nouveau needs to parse the IFR header.

The commit also falsely claimed that there is no graphics (GR) engine.

So rather than try to fix that commit, just revert it and start over
from scratch.

Signed-off-by: default avatarTimur Tabi <ttabi@nvidia.com>
Link: https://patch.msgid.link/20260430223838.2530778-2-ttabi@nvidia.com


Signed-off-by: default avatarDanilo Krummrich <dakr@kernel.org>
parent 7dd57d7a
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+9 −2
Original line number Diff line number Diff line
@@ -2513,6 +2513,7 @@ static const struct nvkm_device_chip
nv170_chipset = {
	.name = "GA100",
	.bar      = { 0x00000001, tu102_bar_new },
	.bios     = { 0x00000001, nvkm_bios_new },
	.devinit  = { 0x00000001, ga100_devinit_new },
	.fault    = { 0x00000001, tu102_fault_new },
	.fb       = { 0x00000001, ga100_fb_new },
@@ -2529,7 +2530,6 @@ nv170_chipset = {
	.vfn      = { 0x00000001, ga100_vfn_new },
	.ce       = { 0x000003ff, ga100_ce_new },
	.fifo     = { 0x00000001, ga100_fifo_new },
	.sec2     = { 0x00000001, tu102_sec2_new },
};

static const struct nvkm_device_chip
@@ -3341,7 +3341,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
	case 0x166: device->chip = &nv166_chipset; break;
	case 0x167: device->chip = &nv167_chipset; break;
	case 0x168: device->chip = &nv168_chipset; break;
	case 0x170: device->chip = &nv170_chipset; break;
	case 0x172: device->chip = &nv172_chipset; break;
	case 0x173: device->chip = &nv173_chipset; break;
	case 0x174: device->chip = &nv174_chipset; break;
@@ -3361,6 +3360,14 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
	case 0x1b6: device->chip = &nv1b6_chipset; break;
	case 0x1b7: device->chip = &nv1b7_chipset; break;
	default:
		if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) {
			switch (device->chipset) {
			case 0x170: device->chip = &nv170_chipset; break;
			default:
				break;
			}
		}

		if (!device->chip) {
			nvdev_error(device, "unknown chipset (%08x)\n", boot0);
			ret = -ENODEV;
+4 −0
Original line number Diff line number Diff line
@@ -41,11 +41,15 @@ ga100_gsp_flcn = {
static const struct nvkm_gsp_func
ga100_gsp = {
	.flcn = &ga100_gsp_flcn,
	.fwsec = &tu102_gsp_fwsec,

	.sig_section = ".fwsignature_ga100",

	.booter.ctor = tu102_gsp_booter_ctor,

	.fwsec_sb.ctor = tu102_gsp_fwsec_sb_ctor,
	.fwsec_sb.dtor = tu102_gsp_fwsec_sb_dtor,

	.dtor = r535_gsp_dtor,
	.oneinit = tu102_gsp_oneinit,
	.init = tu102_gsp_init,
+5 −13
Original line number Diff line number Diff line
@@ -318,13 +318,8 @@ tu102_gsp_oneinit(struct nvkm_gsp *gsp)
	if (ret)
		return ret;

	/*
	 * Calculate FB layout. FRTS is a memory region created by the FWSEC-FRTS firmware.
	 * FWSEC comes from VBIOS.  So on systems with no VBIOS (e.g. GA100), the FRTS does
	 * not exist.  Therefore, use the existence of VBIOS to determine whether to reserve
	 * an FRTS region.
	 */
	gsp->fb.wpr2.frts.size = device->bios ? 0x100000 : 0;
	/* Calculate FB layout. */
	gsp->fb.wpr2.frts.size = 0x100000;
	gsp->fb.wpr2.frts.addr = ALIGN_DOWN(gsp->fb.bios.addr, 0x20000) - gsp->fb.wpr2.frts.size;

	gsp->fb.wpr2.boot.size = gsp->boot.fw.size;
@@ -348,12 +343,9 @@ tu102_gsp_oneinit(struct nvkm_gsp *gsp)
	if (ret)
		return ret;

	/* Only boot FWSEC-FRTS if it actually exists */
	if (gsp->fb.wpr2.frts.size) {
	ret = nvkm_gsp_fwsec_frts(gsp);
	if (WARN_ON(ret))
		return ret;
	}

	/* Reset GSP into RISC-V mode. */
	ret = gsp->func->reset(gsp);