Commit c9edcc18 authored by Yifan Zhang's avatar Yifan Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: update ATHUB_MISC_CNTL offset for athub v3.3 



This patch to update ATHUB_MISC_CNTL offset for athub v3.3

v2: correct a typo (Tim)
v3: correct patch title (Lang)

Signed-off-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarTim Huang <Tim.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8f8cb712

drivers/gpu/drm/amd/amdgpu/athub_v3_0.c

+8 −0
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ 


#define regATHUB_MISC_CNTL_V3_0_1			0x00d7

#define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX		0

#define regATHUB_MISC_CNTL_V3_3_0			0x00d8

#define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX		0





static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)
@@ -40,6 +42,9 @@ static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev) 
	case IP_VERSION(3, 0, 1):

		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);

		break;

	case IP_VERSION(3, 3, 0):

		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0);

		break;

	default:

		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);

		break;
@@ -53,6 +58,9 @@ static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data) 
	case IP_VERSION(3, 0, 1):

		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data);

		break;

	case IP_VERSION(3, 3, 0):

		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0, data);

		break;

	default:

		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);

		break;