Unverified Commit ca35b5b1 authored by Clément Léger's avatar Clément Léger Committed by Palmer Dabbelt
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riscv: hwprobe: export vector crypto ISA extensions 

Export Zv* vector crypto ISA extensions that were added in "RISC-V
Cryptography Extensions Volume II" specification[1] through hwprobe.
This adds support for the following instructions:

- Zvbb: Vector Basic Bit-manipulation
- Zvbc: Vector Carryless Multiplication
- Zvkb: Vector Cryptography Bit-manipulation
- Zvkg: Vector GCM/GMAC.
- Zvkned: NIST Suite: Vector AES Block Cipher
- Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash
- Zvksed: ShangMi Suite: SM4 Block Cipher
- Zvksh: ShangMi Suite: SM3 Secure Hash
- Zvknc: NIST Algorithm Suite with carryless multiply
- Zvkng: NIST Algorithm Suite with GCM.
- Zvksc: ShangMi Algorithm Suite with carryless multiplication
- Zvksg: ShangMi Algorithm Suite with GCM.
- Zvkt: Vector Data-Independent Execution Latency.

Zvkn and Zvks are ommited since they are a superset of other extensions.

Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view

 [1]
Signed-off-by: default avatarClément Léger <cleger@rivosinc.com>
Reviewed-by: default avatarEvan Green <evan@rivosinc.com>
Link: https://lore.kernel.org/r/20231114141256.126749-8-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent aec33539

Documentation/arch/riscv/hwprobe.rst

+30 −0
Original line number Diff line number Diff line
@@ -110,6 +110,36 @@ The following keys are defined: 
  * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined

       in version 1.0 of the Scalar Crypto ISA extensions.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as

       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as

       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as

       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as

       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as

       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as

       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as

       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as

       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as

       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as

       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/uapi/asm/hwprobe.h

+10 −0
Original line number Diff line number Diff line
@@ -40,6 +40,16 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZKSED		(1 << 14)

#define		RISCV_HWPROBE_EXT_ZKSH		(1 << 15)

#define		RISCV_HWPROBE_EXT_ZKT		(1 << 16)

#define		RISCV_HWPROBE_EXT_ZVBB		(1 << 17)

#define		RISCV_HWPROBE_EXT_ZVBC		(1 << 18)

#define		RISCV_HWPROBE_EXT_ZVKB		(1 << 19)

#define		RISCV_HWPROBE_EXT_ZVKG		(1 << 20)

#define		RISCV_HWPROBE_EXT_ZVKNED	(1 << 21)

#define		RISCV_HWPROBE_EXT_ZVKNHA	(1 << 22)

#define		RISCV_HWPROBE_EXT_ZVKNHB	(1 << 23)

#define		RISCV_HWPROBE_EXT_ZVKSED	(1 << 24)

#define		RISCV_HWPROBE_EXT_ZVKSH		(1 << 25)

#define		RISCV_HWPROBE_EXT_ZVKT		(1 << 26)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/sys_riscv.c

+13 −0
Original line number Diff line number Diff line
@@ -173,6 +173,19 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZKSED);

		EXT_KEY(ZKSH);

		EXT_KEY(ZKT);



		if (has_vector()) {

			EXT_KEY(ZVBB);

			EXT_KEY(ZVBC);

			EXT_KEY(ZVKB);

			EXT_KEY(ZVKG);

			EXT_KEY(ZVKNED);

			EXT_KEY(ZVKNHA);

			EXT_KEY(ZVKNHB);

			EXT_KEY(ZVKSED);

			EXT_KEY(ZVKSH);

			EXT_KEY(ZVKT);

		}

#undef EXT_KEY

	}