Commit ca525d53 authored by Anup Patel's avatar Anup Patel Committed by Paul Walmsley
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RISC-V: Define pgprot_dmacoherent() for non-coherent devices 



The pgprot_dmacoherent() is used when allocating memory for
non-coherent devices and by default pgprot_dmacoherent() is
same as pgprot_noncached() unless architecture overrides it.

Currently, there is no pgprot_dmacoherent() definition for
RISC-V hence non-coherent device memory is being mapped as
IO thereby making CPU access to such memory slow.

Define pgprot_dmacoherent() to be same as pgprot_writecombine()
for RISC-V so that CPU access non-coherent device memory as
NOCACHE which is better than accessing it as IO.

Fixes: ff689fd2 ("riscv: add RISC-V Svpbmt extension support")
Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Tested-by: default avatarHan Gao <rabenda.cn@gmail.com>
Tested-by: default avatarGuo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
Link: https://lore.kernel.org/r/20250820152316.1012757-1-apatel@ventanamicro.com


Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent fe69107e

arch/riscv/include/asm/pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -654,6 +654,8 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) 
	return __pgprot(prot);

}



#define pgprot_dmacoherent pgprot_writecombine



/*

 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By

 * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in