Commit ca7a1d0d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2024-02-27-1' of... 

Merge tag 'drm-intel-next-2024-02-27-1' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

drm/i915 feature pull #2 for v6.9:

Features and functionality:
- DP tunneling and bandwidth allocation support (Imre)
- Add more ADL-N PCI IDs (Gustavo)
- Enable fastboot also on older platforms (Ville)
- Bigjoiner force enable debugfs option for testing (Stan)

Refactoring and cleanups:
- Remove unused structs and struct members (Jiri Slaby)
- Use per-device debug logging (Ville)
- State check improvements (Ville)
- Hardcoded cd2x divider cleanups (Ville)
- CDCLK documentation updates (Ville, Rodrigo)

Fixes:
- HDCP MST Type1 fixes (Suraj)
- Fix MTL C20 PHY PLL values (Ravi)
- More hardware access prevention during init (Imre)
- Always enable decompression with tile4 on Xe2 (Juha-Pekka)
- Improve LNL package C residency (Suraj)

drm core changes:
- DP tunneling and bandwidth allocation helpers (Imre)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87sf1devbj.fsf@intel.com
parents 3fe262ec e60cff45

drivers/gpu/drm/display/Kconfig

+21 −0
Original line number Diff line number Diff line
@@ -17,6 +17,27 @@ config DRM_DISPLAY_DP_HELPER 
	help

	  DRM display helpers for DisplayPort.



config DRM_DISPLAY_DP_TUNNEL

	bool

	select DRM_DISPLAY_DP_HELPER

	help

	  Enable support for DisplayPort tunnels. This allows drivers to use

	  DP tunnel features like the Bandwidth Allocation mode to maximize the

	  BW utilization for display streams on Thunderbolt links.



config DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE

	bool "Enable debugging the DP tunnel state"

	depends on REF_TRACKER

	depends on DRM_DISPLAY_DP_TUNNEL

	depends on DEBUG_KERNEL

	depends on EXPERT

	help

	  Enables debugging the DP tunnel manager's state, including the

	  consistency of all managed tunnels' reference counting and the state of

	  streams contained in tunnels.



	  If in doubt, say "N".



config DRM_DISPLAY_HDCP_HELPER

	bool

	depends on DRM_DISPLAY_HELPER

drivers/gpu/drm/display/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_HELPER) += \ 
	drm_dp_helper.o \

	drm_dp_mst_topology.o \

	drm_dsc_helper.o

drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_TUNNEL) += \

	drm_dp_tunnel.o

drm_display_helper-$(CONFIG_DRM_DISPLAY_HDCP_HELPER) += drm_hdcp_helper.o

drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_HELPER) += \

	drm_hdmi_helper.o \

drivers/gpu/drm/display/drm_dp_helper.c

+30 −0
Original line number Diff line number Diff line
@@ -4055,3 +4055,33 @@ int drm_dp_bw_channel_coding_efficiency(bool is_uhbr) 
		return 800000;

}

EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);



/**

 * drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink

 * @max_link_rate: max DPRX link rate in 10kbps units

 * @max_lanes: max DPRX lane count

 *

 * Given a link rate and lanes, get the data bandwidth.

 *

 * Data bandwidth is the actual payload rate, which depends on the data

 * bandwidth efficiency and the link rate.

 *

 * Note that protocol layers above the DPRX link level considered here can

 * further limit the maximum data rate. Such layers are the MST topology (with

 * limits on the link between the source and first branch device as well as on

 * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -

 * which in turn can encapsulate an MST link with its own limit - with each

 * SST or MST encapsulated tunnel sharing the BW of a tunnel group.

 *

 * Returns the maximum data rate in kBps units.

 */

int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes)

{

	int ch_coding_efficiency =

		drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));



	return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,

					      ch_coding_efficiency),

				  1000000 * 8);

}

EXPORT_SYMBOL(drm_dp_max_dprx_data_rate);

drivers/gpu/drm/display/drm_dp_tunnel.c

0 → 100644
+1949 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -155,6 +155,20 @@ config DRM_I915_PXP 
	  protected session and manage the status of the alive software session,

	  as well as its life cycle.



config DRM_I915_DP_TUNNEL

	bool "Enable DP tunnel support"

	depends on DRM_I915

	depends on USB4

	select DRM_DISPLAY_DP_TUNNEL

	default y

	help

	  Choose this option to detect DP tunnels and enable the Bandwidth

	  Allocation mode for such tunnels. This allows using the maximum

	  resolution allowed by the link BW on all displays sharing the

	  link BW, for instance on a Thunderbolt link.



	  If in doubt, say "Y".



menu "drm/i915 Debugging"

depends on DRM_I915

depends on EXPERT