Commit ca7a7518 authored by Asad Kamal's avatar Asad Kamal Committed by Alex Deucher
Browse files

drm/amd/pm: Add SMUv13.0.12 PPT interface 



Add SMUv13.0.12 PPT interface to fetch dpm features

Signed-off-by: default avatarAsad Kamal <asad.kamal@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 00117e3e

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

0 → 100644
+138 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef SMU_13_0_12_PMFW_H

#define SMU_13_0_12_PMFW_H



#define NUM_VCLK_DPM_LEVELS   4

#define NUM_DCLK_DPM_LEVELS   4

#define NUM_SOCCLK_DPM_LEVELS 4

#define NUM_LCLK_DPM_LEVELS   4

#define NUM_UCLK_DPM_LEVELS   4

#define NUM_FCLK_DPM_LEVELS   4

#define NUM_XGMI_DPM_LEVELS   2

#define NUM_CXL_BITRATES      4

#define NUM_PCIE_BITRATES     4

#define NUM_XGMI_BITRATES     4

#define NUM_XGMI_WIDTHS       3

#define NUM_TDP_GROUPS        4

#define NUM_SOC_P2S_TABLES    6

#define NUM_GFX_P2S_TABLES    8

#define NUM_PSM_DIDT_THRESHOLDS 3



typedef enum {

/*0*/   FEATURE_DATA_CALCULATION            = 0,

/*1*/   FEATURE_DPM_FCLK                    = 1,

/*2*/   FEATURE_DPM_GFXCLK                  = 2,

/*3*/   FEATURE_DPM_LCLK                    = 3,

/*4*/   FEATURE_DPM_SOCCLK                  = 4,

/*5*/   FEATURE_DPM_UCLK                    = 5,

/*6*/   FEATURE_DPM_VCN                     = 6,

/*7*/   FEATURE_DPM_XGMI                    = 7,

/*8*/   FEATURE_DS_FCLK                     = 8,

/*9*/   FEATURE_DS_GFXCLK                   = 9,

/*10*/  FEATURE_DS_LCLK                     = 10,

/*11*/  FEATURE_DS_MP0CLK                   = 11,

/*12*/  FEATURE_DS_MP1CLK                   = 12,

/*13*/  FEATURE_DS_MPIOCLK                  = 13,

/*14*/  FEATURE_DS_SOCCLK                   = 14,

/*15*/  FEATURE_DS_VCN                      = 15,

/*16*/  FEATURE_APCC_DFLL                   = 16,

/*17*/  FEATURE_APCC_PLUS                   = 17,

/*18*/  FEATURE_PPT                         = 18,

/*19*/  FEATURE_TDC                         = 19,

/*20*/  FEATURE_THERMAL                     = 20,

/*21*/  FEATURE_SOC_PCC                     = 21,

/*22*/  FEATURE_PROCHOT                     = 22,

/*23*/  FEATURE_FDD_AID_HBM                 = 23,

/*24*/  FEATURE_FDD_AID_SOC                 = 24,

/*25*/  FEATURE_FDD_XCD_EDC                 = 25,

/*26*/  FEATURE_FDD_XCD_XVMIN               = 26,

/*27*/  FEATURE_FW_CTF                      = 27,

/*28*/  FEATURE_SMU_CG                      = 28,

/*29*/  FEATURE_PSI7                        = 29,

/*30*/  FEATURE_XGMI_PER_LINK_PWR_DOWN      = 30,

/*31*/  FEATURE_SOC_DC_RTC                  = 31,

/*32*/  FEATURE_GFX_DC_RTC                  = 32,

/*33*/  FEATURE_DVM_MIN_PSM                 = 33,

/*34*/  FEATURE_PRC                         = 34,

/*35*/  FEATURE_PSM_SQ_THROTTLER            = 35,

/*36*/  FEATURE_PIT                         = 36,

/*37*/  FEATURE_DVO                         = 37,

/*38*/  FEATURE_XVMINORPSM_CLKSTOP_DS       = 38,



/*39*/  NUM_FEATURES                        = 39

} FEATURE_LIST_e;



//enum for MPIO PCIe gen speed msgs

typedef enum {

  PCIE_LINK_SPEED_INDEX_TABLE_GEN1,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN2,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN3,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN4,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN4_ESM,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN5,

  PCIE_LINK_SPEED_INDEX_TABLE_COUNT

} PCIE_LINK_SPEED_INDEX_TABLE_e;



typedef enum {

  GFX_GUARDBAND_OFFSET_0,

  GFX_GUARDBAND_OFFSET_1,

  GFX_GUARDBAND_OFFSET_2,

  GFX_GUARDBAND_OFFSET_3,

  GFX_GUARDBAND_OFFSET_4,

  GFX_GUARDBAND_OFFSET_5,

  GFX_GUARDBAND_OFFSET_6,

  GFX_GUARDBAND_OFFSET_7,

  GFX_GUARDBAND_OFFSET_COUNT

} GFX_GUARDBAND_OFFSET_e;



typedef enum {

  GFX_DVM_MARGINHI_0,

  GFX_DVM_MARGINHI_1,

  GFX_DVM_MARGINHI_2,

  GFX_DVM_MARGINHI_3,

  GFX_DVM_MARGINHI_4,

  GFX_DVM_MARGINHI_5,

  GFX_DVM_MARGINHI_6,

  GFX_DVM_MARGINHI_7,

  GFX_DVM_MARGINLO_0,

  GFX_DVM_MARGINLO_1,

  GFX_DVM_MARGINLO_2,

  GFX_DVM_MARGINLO_3,

  GFX_DVM_MARGINLO_4,

  GFX_DVM_MARGINLO_5,

  GFX_DVM_MARGINLO_6,

  GFX_DVM_MARGINLO_7,

  GFX_DVM_MARGIN_COUNT

} GFX_DVM_MARGIN_e;



#define SMU_VF_METRICS_TABLE_VERSION 0x3



typedef struct __attribute__((packed, aligned(4))) {

  uint32_t AccumulationCounter;

  uint32_t InstGfxclk_TargFreq;

  uint64_t AccGfxclk_TargFreq;

  uint64_t AccGfxRsmuDpm_Busy;

} VfMetricsTable_t;



#endif

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

+2 −0
Original line number Diff line number Diff line
@@ -306,5 +306,7 @@ int smu_v13_0_get_boot_freq_by_index(struct smu_context *smu, 
				     uint32_t *value);



void smu_v13_0_interrupt_work(struct smu_context *smu);

bool smu_v13_0_12_is_dpm_running(struct smu_context *smu);

extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[];

#endif

#endif

drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 
# It provides the smu management services for the driver.



SMU13_MGR = smu_v13_0.o aldebaran_ppt.o yellow_carp_ppt.o smu_v13_0_0_ppt.o smu_v13_0_4_ppt.o \

	    smu_v13_0_5_ppt.o smu_v13_0_7_ppt.o smu_v13_0_6_ppt.o

	    smu_v13_0_5_ppt.o smu_v13_0_7_ppt.o smu_v13_0_6_ppt.o smu_v13_0_12_ppt.o



AMD_SWSMU_SMU13MGR = $(addprefix $(AMD_SWSMU_PATH)/smu13/,$(SMU13_MGR))

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

0 → 100644
+101 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#define SWSMU_CODE_LAYER_L2



#include <linux/firmware.h>

#include "amdgpu.h"

#include "amdgpu_smu.h"

#include "smu_v13_0_12_pmfw.h"

#include "smu_v13_0_6_ppt.h"

#include "smu_v13_0.h"

#include "amdgpu_xgmi.h"

#include <linux/pci.h>

#include "smu_cmn.h"



#undef MP1_Public

#undef smnMP1_FIRMWARE_FLAGS



/*

 * DO NOT use these for err/warn/info/debug messages.

 * Use dev_err, dev_warn, dev_info and dev_dbg instead.

 * They are more MGPU friendly.

 */

#undef pr_err

#undef pr_warn

#undef pr_info

#undef pr_debug



#define SMU_13_0_12_FEA_MAP(smu_feature, smu_13_0_12_feature)                    \

	[smu_feature] = { 1, (smu_13_0_12_feature) }



#define FEATURE_MASK(feature) (1ULL << feature)

#define SMC_DPM_FEATURE                                                        \

	(FEATURE_MASK(FEATURE_DATA_CALCULATION) |                              \

	 FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_FCLK))



const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[SMU_FEATURE_COUNT] = {

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, 		FEATURE_DATA_CALCULATION),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, 		FEATURE_DPM_GFXCLK),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, 			FEATURE_DPM_FCLK),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, 			FEATURE_DS_GFXCLK),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, 			FEATURE_DS_SOCCLK),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, 			FEATURE_DS_LCLK),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, 			FEATURE_DS_FCLK),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_PPT_BIT, 			FEATURE_PPT),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_TDC_BIT, 			FEATURE_TDC),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, 			FEATURE_APCC_DFLL),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, 			FEATURE_SMU_CG),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, 			FEATURE_FW_CTF),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_THERMAL_BIT, 			FEATURE_THERMAL),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_SOC_PCC_BIT, 			FEATURE_SOC_PCC),

	SMU_13_0_12_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,	FEATURE_XGMI_PER_LINK_PWR_DOWN),

};



static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu,

					 uint64_t *feature_mask)

{

	int ret;



	ret = smu_cmn_get_enabled_mask(smu, feature_mask);



	if (ret == -EIO) {

		*feature_mask = 0;

		ret = 0;

	}



	return ret;

}



bool smu_v13_0_12_is_dpm_running(struct smu_context *smu)

{

	int ret;

	uint64_t feature_enabled;



	ret = smu_v13_0_12_get_enabled_mask(smu, &feature_enabled);



	if (ret)

		return false;



	return !!(feature_enabled & SMC_DPM_FEATURE);

}

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

+5 −1
Original line number Diff line number Diff line
@@ -2193,6 +2193,9 @@ static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu) 
	int ret;

	uint64_t feature_enabled;



	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))

		return smu_v13_0_12_is_dpm_running(smu);



	ret = smu_v13_0_6_get_enabled_mask(smu, &feature_enabled);



	if (ret)
@@ -3564,7 +3567,8 @@ void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) 
	smu->ppt_funcs = &smu_v13_0_6_ppt_funcs;

	smu->message_map = smu_v13_0_6_message_map;

	smu->clock_map = smu_v13_0_6_clk_map;

	smu->feature_map = smu_v13_0_6_feature_mask_map;

	smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?

		smu_v13_0_12_feature_mask_map : smu_v13_0_6_feature_mask_map;

	smu->table_map = smu_v13_0_6_table_map;

	smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION;

	smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;