Commit ca8179ba authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Update phantom pipe enable / disable sequence 



Previously we would call apply_ctx_to_hw to enable and disable
phantom pipes. However, apply_ctx_to_hw can potentially update
non-phantom pipes as well which is undesired. Instead of calling
apply_ctx_to_hw as a whole, call the relevant helpers for each
phantom pipe when enabling / disabling which will avoid us modifying
hardware state for non-phantom pipes unknowingly.

The use case is for an FRL display where FRL_Update is requested
by the display. In this case link_state_valid flag is cleared in
a passive callback thread and should be handled in the next stream /
link update. However, due to the call to apply_ctx_to_hw for the
phantom pipes during a flip, the main pipes were modified outside
of the desired sequence (driver does not handle link_state_valid = 0
on flips).

Cc: stable@vger.kernel.org # 6.6+
Reviewed-by: default avatarSamson Tam <samson.tam@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e6a7df96

drivers/gpu/drm/amd/display/dc/core/dc.c

+3 −1
Original line number Diff line number Diff line
@@ -3817,7 +3817,9 @@ static void commit_planes_for_stream(struct dc *dc, 
		 * programming has completed (we turn on phantom OTG in order

		 * to complete the plane disable for phantom pipes).

		 */

		dc->hwss.apply_ctx_to_hw(dc, context);



		if (dc->hwss.disable_phantom_streams)

			dc->hwss.disable_phantom_streams(dc, context);

	}



	if (update_type != UPDATE_TYPE_FAST)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

+2 −2
Original line number Diff line number Diff line
@@ -1476,7 +1476,7 @@ static enum dc_status dce110_enable_stream_timing( 
	return DC_OK;

}



static enum dc_status apply_single_controller_ctx_to_hw(

enum dc_status dce110_apply_single_controller_ctx_to_hw(

		struct pipe_ctx *pipe_ctx,

		struct dc_state *context,

		struct dc *dc)
@@ -2302,7 +2302,7 @@ enum dc_status dce110_apply_ctx_to_hw( 
		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)

			continue;



		status = apply_single_controller_ctx_to_hw(

		status = dce110_apply_single_controller_ctx_to_hw(

				pipe_ctx,

				context,

				dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

+4 −0
Original line number Diff line number Diff line
@@ -39,6 +39,10 @@ enum dc_status dce110_apply_ctx_to_hw( 
		struct dc *dc,

		struct dc_state *context);



enum dc_status dce110_apply_single_controller_ctx_to_hw(

		struct pipe_ctx *pipe_ctx,

		struct dc_state *context,

		struct dc *dc);



void dce110_enable_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

+1 −1
Original line number Diff line number Diff line
@@ -2561,7 +2561,7 @@ void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 
		tg->funcs->setup_vertical_interrupt2(tg, start_line);

}



static void dcn20_reset_back_end_for_pipe(

void dcn20_reset_back_end_for_pipe(

		struct dc *dc,

		struct pipe_ctx *pipe_ctx,

		struct dc_state *context)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

+4 −0
Original line number Diff line number Diff line
@@ -84,6 +84,10 @@ enum dc_status dcn20_enable_stream_timing( 
void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

void dcn20_reset_back_end_for_pipe(

		struct dc *dc,

		struct pipe_ctx *pipe_ctx,

		struct dc_state *context);

void dcn20_init_blank(

		struct dc *dc,

		struct timing_generator *tg);