Commit caae599d authored by Keerthy's avatar Keerthy Committed by Vignesh Raghavendra
Browse files

arm64: dts: ti: k3-j784s4-main: Add the main domain watchdog instances 



There are totally 19 instances of watchdog module. One each for the
8 A72 cores, one each for the 4 C7x cores, 1 for the GPU, 1 each
for the 6 R5F cores in the main domain. The non-A72 instances are
coupled with the R5Fs, C7x & GPU instances. Keeping them as reserved as
they are not used by A72.

Signed-off-by: default avatarKeerthy <j-keerthy@ti.com>
Link: https://lore.kernel.org/r/20231008044657.25788-5-j-keerthy@ti.com


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 81be795b

arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi

+198 −0
Original line number Diff line number Diff line
@@ -1593,4 +1593,202 @@ main_esm: esm@700000 { 
			      <695>;

		bootph-pre-ram;

	};



	watchdog0: watchdog@2200000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2200000 0x00 0x100>;

		clocks = <&k3_clks 348 1>;

		power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 348 0>;

		assigned-clock-parents = <&k3_clks 348 4>;

	};



	watchdog1: watchdog@2210000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2210000 0x00 0x100>;

		clocks = <&k3_clks 349 1>;

		power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 349 0>;

		assigned-clock-parents = <&k3_clks 349 4>;

	};



	watchdog2: watchdog@2220000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2220000 0x00 0x100>;

		clocks = <&k3_clks 350 1>;

		power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 350 0>;

		assigned-clock-parents = <&k3_clks 350 4>;

	};



	watchdog3: watchdog@2230000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2230000 0x00 0x100>;

		clocks = <&k3_clks 351 1>;

		power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 351 0>;

		assigned-clock-parents = <&k3_clks 351 4>;

	};



	watchdog4: watchdog@2240000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2240000 0x00 0x100>;

		clocks = <&k3_clks 352 1>;

		power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 352 0>;

		assigned-clock-parents = <&k3_clks 352 4>;

	};



	watchdog5: watchdog@2250000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2250000 0x00 0x100>;

		clocks = <&k3_clks 353 1>;

		power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 353 0>;

		assigned-clock-parents = <&k3_clks 353 4>;

	};



	watchdog6: watchdog@2260000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2260000 0x00 0x100>;

		clocks = <&k3_clks 354 1>;

		power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 354 0>;

		assigned-clock-parents = <&k3_clks 354 4>;

	};



	watchdog7: watchdog@2270000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2270000 0x00 0x100>;

		clocks = <&k3_clks 355 1>;

		power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 355 0>;

		assigned-clock-parents = <&k3_clks 355 4>;

	};



	/*

	 * The following RTI instances are coupled with MCU R5Fs, c7x and

	 * GPU so keeping them reserved as these will be used by their

	 * respective firmware

	 */

	watchdog8: watchdog@22f0000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x22f0000 0x00 0x100>;

		clocks = <&k3_clks 360 1>;

		power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 360 0>;

		assigned-clock-parents = <&k3_clks 360 4>;

		/* reserved for GPU */

		status = "reserved";

	};



	watchdog9: watchdog@2300000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2300000 0x00 0x100>;

		clocks = <&k3_clks 356 1>;

		power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 356 0>;

		assigned-clock-parents = <&k3_clks 356 4>;

		/* reserved for C7X_0 DSP */

		status = "reserved";

	};



	watchdog10: watchdog@2310000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2310000 0x00 0x100>;

		clocks = <&k3_clks 357 1>;

		power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 357 0>;

		assigned-clock-parents = <&k3_clks 357 4>;

		/* reserved for C7X_1 DSP */

		status = "reserved";

	};



	watchdog11: watchdog@2320000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2320000 0x00 0x100>;

		clocks = <&k3_clks 358 1>;

		power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 358 0>;

		assigned-clock-parents = <&k3_clks 358 4>;

		/* reserved for C7X_2 DSP */

		status = "reserved";

	};



	watchdog12: watchdog@2330000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2330000 0x00 0x100>;

		clocks = <&k3_clks 359 1>;

		power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 359 0>;

		assigned-clock-parents = <&k3_clks 359 4>;

		/* reserved for C7X_3 DSP */

		status = "reserved";

	};



	watchdog13: watchdog@23c0000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x23c0000 0x00 0x100>;

		clocks = <&k3_clks 361 1>;

		power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 361 0>;

		assigned-clock-parents = <&k3_clks 361 4>;

		/* reserved for MAIN_R5F0_0 */

		status = "reserved";

	};



	watchdog14: watchdog@23d0000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x23d0000 0x00 0x100>;

		clocks = <&k3_clks 362 1>;

		power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 362 0>;

		assigned-clock-parents = <&k3_clks 362 4>;

		/* reserved for MAIN_R5F0_1 */

		status = "reserved";

	};



	watchdog15: watchdog@23e0000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x23e0000 0x00 0x100>;

		clocks = <&k3_clks 363 1>;

		power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 363 0>;

		assigned-clock-parents = <&k3_clks 363 4>;

		/* reserved for MAIN_R5F1_0 */

		status = "reserved";

	};



	watchdog16: watchdog@23f0000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x23f0000 0x00 0x100>;

		clocks = <&k3_clks 364 1>;

		power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 364 0>;

		assigned-clock-parents = <&k3_clks 364 4>;

		/* reserved for MAIN_R5F1_1 */

		status = "reserved";

	};



	watchdog17: watchdog@2540000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2540000 0x00 0x100>;

		clocks = <&k3_clks 365 1>;

		power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 365 0>;

		assigned-clock-parents = <&k3_clks 366 4>;

		/* reserved for MAIN_R5F2_0 */

		status = "reserved";

	};



	watchdog18: watchdog@2550000 {

		compatible = "ti,j7-rti-wdt";

		reg = <0x00 0x2550000 0x00 0x100>;

		clocks = <&k3_clks 366 1>;

		power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 366 0>;

		assigned-clock-parents = <&k3_clks 366 4>;

		/* reserved for MAIN_R5F2_1 */

		status = "reserved";

	};

};