Commit caf5ad18 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

soc: qcom: ubwc: Fix SM6125's ubwc_swizzle value 



The value of 7 (a.k.a. GENMASK(2, 0), a.k.a. disabling levels 1-3 of
swizzling) is what we want on this platform (and others with a UBWC
1.0 encoder).

Fix it to make mesa happy (the hardware doesn't care about the 2 higher
bits, as they weren't consumed on this platform).

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660980/


Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent 8f18e879

drivers/soc/qcom/ubwc_config.c

+1 −1
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ static const struct qcom_ubwc_cfg_data sm6115_data = { 
static const struct qcom_ubwc_cfg_data sm6125_data = {

	.ubwc_enc_version = UBWC_1_0,

	.ubwc_dec_version = UBWC_3_0,

	.ubwc_swizzle = 1,

	.ubwc_swizzle = 7,

	.highest_bank_bit = 14,

};