Commit cb67ff62 authored by Jonathan Kim's avatar Jonathan Kim Committed by Alex Deucher
Browse files

drm/amdkfd: flag per-queue reset support for gfx9



Flag KFD support for per-queue reset on GFX9 devices.

Signed-off-by: default avatarJonathan Kim <jonathan.kim@amd.com>
Reviewed-by: default avatarHarish Kasiviswanathan <harish.kasiviswanathan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7daa0f6b
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+2 −0
Original line number Diff line number Diff line
@@ -1998,6 +1998,8 @@ static void kfd_topology_set_capabilities(struct kfd_topology_device *dev)
		if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(9, 4, 2))
			dev->node_props.capability |=
				HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;

		dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED;
	} else {
		dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |
					HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
+2 −1
Original line number Diff line number Diff line
@@ -60,7 +60,8 @@
#define HSA_CAP_FLAGS_COHERENTHOSTACCESS			0x10000000
#define HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED			0x20000000
#define HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED	0x40000000
#define HSA_CAP_RESERVED					0x800f8000
#define HSA_CAP_PER_QUEUE_RESET_SUPPORTED			0x80000000
#define HSA_CAP_RESERVED					0x000f8000

/* debug_prop bits in node properties */
#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_MASK     0x0000000f