Commit cb7a978c authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: DPP low mem pwr related adjustment -Part I 



[why]
Default low pwr mem state get chagned.
SW needs to wake mem up first
also need to put back to LS again after use: will do in Part II.

Reviewed-by: default avatarLeo Chen <leo.chen@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarChenyu Chen <chen-yu.chen@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8ae9d73b

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

+1 −0
Original line number Diff line number Diff line
@@ -545,6 +545,7 @@ 
	type SCL_COEF_RAM_SELECT_CURRENT; \

	type LUT_MEM_PWR_FORCE; \

	type LUT_MEM_PWR_STATE; \

	type LUT_MEM_PWR_DIS; \

	type CM_GAMUT_REMAP_MODE; \

	type CM_GAMUT_REMAP_C11; \

	type CM_GAMUT_REMAP_C12; \

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

+9 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ 
	TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\

	TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\

	TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\

	TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\

	TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\

	TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\

	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\
@@ -208,6 +209,7 @@ 
	TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\

	TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\

	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\

	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_DIS, mask_sh),\

	TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh),\

	TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_MATRIX_MODE, mask_sh),\

	TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_LTONL_EN, mask_sh),\
@@ -336,6 +338,9 @@ 
	TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C2, mask_sh),\

	TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C3, mask_sh),\

	TF_SF(DSCL0_ISHARP_DELTA_CTRL, ISHARP_DELTA_LUT_HOST_SELECT, mask_sh),\

	TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_DIS, mask_sh),\

	TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_FORCE, mask_sh),\

	TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_STATE, mask_sh),\

	TF_SF(DSCL0_ISHARP_DELTA_DATA, ISHARP_DELTA_DATA, mask_sh),\

	TF_SF(DSCL0_ISHARP_DELTA_INDEX, ISHARP_DELTA_INDEX, mask_sh),\

	TF_SF(DSCL0_ISHARP_MODE, ISHARP_EN, mask_sh),\
@@ -558,6 +563,9 @@ 
	type ISHARP_DELTA_LUT_SELECT;	\

	type ISHARP_DELTA_LUT_SELECT_CURRENT;	\

	type ISHARP_DELTA_LUT_HOST_SELECT;	\

	type ISHARP_DELTA_LUT_MEM_PWR_DIS;	\

	type ISHARP_DELTA_LUT_MEM_PWR_FORCE;\

	type ISHARP_DELTA_LUT_MEM_PWR_STATE;\

	type ISHARP_DELTA_DATA;	\

	type ISHARP_DELTA_INDEX; \

	type ISHARP_NLDELTA_SCLIP_EN_P;	\
@@ -629,6 +637,7 @@ 
	uint32_t DSCL_SC_MATRIX_C0C1; \

	uint32_t DSCL_SC_MATRIX_C2C3; \

	uint32_t ISHARP_MODE; \

	uint32_t ISHARP_DELTA_LUT_MEM_PWR_CTRL; \

	uint32_t ISHARP_NOISEDET_THRESHOLD; \

	uint32_t ISHARP_NOISE_GAIN_PWL; \

	uint32_t ISHARP_LBA_PWL_SEG0; \

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

+49 −53
Original line number Diff line number Diff line
@@ -966,11 +966,7 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, 
		ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm);



	/* Skip remaining register programming if ISHARP is disabled */

	if (!scl_data->dscl_prog_data.isharp_en) {

		PERF_TRACE();

		return;

	}



	if (scl_data->dscl_prog_data.isharp_en) {

		/* ISHARP_NOISEDET_THRESHOLD */

		REG_SET_2(ISHARP_NOISEDET_THRESHOLD, 0,

			ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold,
@@ -1021,7 +1017,6 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, 
			ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n);



	/* Blur and Scale Coefficients - SCL_COEF_RAM_TAP_SELECT */

	if (scl_data->dscl_prog_data.isharp_en) {

		if (scl_data->dscl_prog_data.filter_blur_scale_v) {

			dpp401_dscl_set_scaler_filter(

				dpp, scl_data->taps.v_taps,
@@ -1037,6 +1032,7 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, 
			*bs_coeffs_updated = true;

		}

	}



	PERF_TRACE();

} // dpp401_dscl_program_isharp

/**

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

+1 −0
Original line number Diff line number Diff line
@@ -394,6 +394,7 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); 
	SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id),                                  \

	SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id),                                  \

	SRI_ARR(ISHARP_MODE, DSCL, id),                                          \

	SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id),                                          \

	SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id),                            \

	SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id),                                \

	SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id),                                  \