Commit cbbd05d0 authored by Randy Dunlap's avatar Randy Dunlap Committed by Dan Williams
Browse files

cxl: fix spelling mistakes 



Correct spelling mistakes (reported by codespell).

Signed-off-by: default avatarRandy Dunlap <rdunlap@infradead.org>
Cc: Alison Schofield <alison.schofield@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Cc: Ben Widawsky <bwidawsk@kernel.org>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org
Reviewed-by: default avatarVishal Verma <vishal.l.verma@intel.com>
Reviewed-by: default avatarAlison Schofield <alison.schofield@intel.com>
Link: https://lore.kernel.org/r/20230125032221.21277-1-rdunlap@infradead.org


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 66f3cb79

drivers/cxl/Kconfig

+1 −1
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@@ -116,7 +116,7 @@ config CXL_REGION_INVALIDATION_TEST 
	depends on CXL_REGION

	help

	  CXL Region management and security operations potentially invalidate

	  the content of CPU caches without notifiying those caches to

	  the content of CPU caches without notifying those caches to

	  invalidate the affected cachelines. The CXL Region driver attempts

	  to invalidate caches when those events occur.  If that invalidation

	  fails the region will fail to enable.  Reasons for cache

drivers/cxl/acpi.c

+1 −1
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@@ -19,7 +19,7 @@ struct cxl_cxims_data { 


/*

 * Find a targets entry (n) in the host bridge interleave list.

 * CXL Specfication 3.0 Table 9-22

 * CXL Specification 3.0 Table 9-22

 */

static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,

			  int ig)

drivers/cxl/core/port.c

+1 −1
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@@ -1164,7 +1164,7 @@ static struct cxl_port *find_cxl_port_at(struct cxl_port *parent_port, 
}



/*

 * All users of grandparent() are using it to walk PCIe-like swich port

 * All users of grandparent() are using it to walk PCIe-like switch port

 * hierarchy. A PCIe switch is comprised of a bridge device representing the

 * upstream switch port and N bridges representing downstream switch ports. When

 * bridges stack the grand-parent of a downstream switch port is another

drivers/cxl/core/region.c

+1 −1
Original line number Diff line number Diff line
@@ -414,7 +414,7 @@ static ssize_t interleave_granularity_store(struct device *dev, 
	 * When the host-bridge is interleaved, disallow region granularity !=

	 * root granularity. Regions with a granularity less than the root

	 * interleave result in needing multiple endpoints to support a single

	 * slot in the interleave (possible to suport in the future). Regions

	 * slot in the interleave (possible to support in the future). Regions

	 * with a granularity greater than the root interleave result in invalid

	 * DPA translations (invalid to support).

	 */