Unverified Commit cbe33705 authored by Larisa Grigore's avatar Larisa Grigore Committed by Mark Brown
Browse files

spi: spi-fsl-lpspi: Set correct chip-select polarity bit 



The driver currently supports multiple chip-selects, but only sets the
polarity for the first one (CS 0). Fix it by setting the PCSPOL bit for
the desired chip-select.

Fixes: 5314987d ("spi: imx: add lpspi bus driver")
Signed-off-by: default avatarLarisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: default avatarJames Clark <james.clark@linaro.org>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-2-6262b9aa9be4@linaro.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 782a7c73

drivers/spi/spi-fsl-lpspi.c

+5 −2
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
// Copyright 2016 Freescale Semiconductor, Inc.

// Copyright 2018, 2023, 2025 NXP



#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/completion.h>

#include <linux/delay.h>
@@ -70,7 +71,7 @@ 
#define DER_TDDE	BIT(0)

#define CFGR1_PCSCFG	BIT(27)

#define CFGR1_PINCFG	(BIT(24)|BIT(25))

#define CFGR1_PCSPOL	BIT(8)

#define CFGR1_PCSPOL_MASK	GENMASK(11, 8)

#define CFGR1_NOSTALL	BIT(3)

#define CFGR1_HOST	BIT(0)

#define FSR_TXCOUNT	(0xFF)
@@ -423,7 +424,9 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) 
	else

		temp = CFGR1_PINCFG;

	if (fsl_lpspi->config.mode & SPI_CS_HIGH)

		temp |= CFGR1_PCSPOL;

		temp |= FIELD_PREP(CFGR1_PCSPOL_MASK,

				   BIT(fsl_lpspi->config.chip_select));



	writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);



	temp = readl(fsl_lpspi->base + IMX7ULP_CR);