Commit cc41f29a authored by Brian Masney's avatar Brian Masney Committed by Dmitry Baryshkov
Browse files

drm/msm/dsi_phy_14nm: convert from round_rate() to determine_rate() 



The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series. The change to use clamp_t() was
done manually.

Signed-off-by: default avatarBrian Masney <bmasney@redhat.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/667869/
Link: https://lore.kernel.org/r/20250810-drm-msm-phy-clk-round-rate-v2-2-0fd1f7979c83@redhat.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent fe3190a3

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+17 −17
Original line number Diff line number Diff line
@@ -578,21 +578,19 @@ static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw) 
	pll_14nm->phy->pll_on = false;

}



static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw,

		unsigned long rate, unsigned long *parent_rate)

static int dsi_pll_14nm_clk_determine_rate(struct clk_hw *hw,

					   struct clk_rate_request *req)

{

	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);



	if      (rate < pll_14nm->phy->cfg->min_pll_rate)

		return  pll_14nm->phy->cfg->min_pll_rate;

	else if (rate > pll_14nm->phy->cfg->max_pll_rate)

		return  pll_14nm->phy->cfg->max_pll_rate;

	else

		return rate;

	req->rate = clamp_t(unsigned long, req->rate,

			    pll_14nm->phy->cfg->min_pll_rate, pll_14nm->phy->cfg->max_pll_rate);



	return 0;

}



static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {

	.round_rate = dsi_pll_14nm_clk_round_rate,

	.determine_rate = dsi_pll_14nm_clk_determine_rate,

	.set_rate = dsi_pll_14nm_vco_set_rate,

	.recalc_rate = dsi_pll_14nm_vco_recalc_rate,

	.prepare = dsi_pll_14nm_vco_prepare,
@@ -622,18 +620,20 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, 
				   postdiv->flags, width);

}



static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,

					    unsigned long rate,

					    unsigned long *prate)

static int dsi_pll_14nm_postdiv_determine_rate(struct clk_hw *hw,

					       struct clk_rate_request *req)

{

	struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);

	struct dsi_pll_14nm *pll_14nm = postdiv->pll;



	DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate);

	DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, req->rate);



	return divider_round_rate(hw, rate, prate, NULL,

	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,

				       NULL,

				       postdiv->width,

				       postdiv->flags);



	return 0;

}



static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -680,7 +680,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 


static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {

	.recalc_rate = dsi_pll_14nm_postdiv_recalc_rate,

	.round_rate = dsi_pll_14nm_postdiv_round_rate,

	.determine_rate = dsi_pll_14nm_postdiv_determine_rate,

	.set_rate = dsi_pll_14nm_postdiv_set_rate,

};