Commit cc520964 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: move build test pattern params as part of pipe resource update for odm 



[why]
Move built test pattern as part of pipe resource update for odm to ensure we rebuild
test pattern params every time we have an ODM update

Reviewed-by: default avatarGeorge Shen <george.shen@amd.com>
Acked-by: default avatarRoman Li <roman.li@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e779f458

drivers/gpu/drm/amd/display/dc/core/dc.c

+15 −9
Original line number Diff line number Diff line
@@ -3235,14 +3235,6 @@ static bool update_planes_and_stream_state(struct dc *dc, 
			BREAK_TO_DEBUGGER();

			goto fail;

		}



		for (i = 0; i < context->stream_count; i++) {

			struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&context->res_ctx,

					context->streams[i]);



			if (otg_master && otg_master->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE)

				resource_build_test_pattern_params(&context->res_ctx, otg_master);

		}

	}

	update_seamless_boot_flags(dc, context, surface_count, stream);
@@ -3338,12 +3330,26 @@ static void commit_planes_do_stream_update(struct dc *dc, 
 			}



			if (stream_update->pending_test_pattern) {

				dc_link_dp_set_test_pattern(stream->link,

				/*

				 * test pattern params depends on ODM topology

				 * changes that we could be applying to front

				 * end. Since at the current stage front end

				 * changes are not yet applied. We can only

				 * apply test pattern in hw based on current

				 * state and populate the final test pattern

				 * params in new state. If current and new test

				 * pattern params are different as result of

				 * different ODM topology being used, it will be

				 * detected and handle during front end

				 * programming update.

				 */

				dc->link_srv->dp_set_test_pattern(stream->link,

					stream->test_pattern.type,

					stream->test_pattern.color_space,

					stream->test_pattern.p_link_settings,

					stream->test_pattern.p_custom_pattern,

					stream->test_pattern.cust_pattern_size);

				resource_build_test_pattern_params(&context->res_ctx, pipe_ctx);

			}



			if (stream_update->dpms_off) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+7 −0
Original line number Diff line number Diff line
@@ -1457,6 +1457,9 @@ void resource_build_test_pattern_params(struct resource_context *res_ctx, 
	controller_color_space = convert_dp_to_controller_color_space(

			otg_master->stream->test_pattern.color_space);



	if (controller_test_pattern == CONTROLLER_DP_TEST_PATTERN_VIDEOMODE)

		return;



	odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, opp_heads);



	odm_slice_width = h_active / odm_cnt;
@@ -2325,6 +2328,9 @@ static bool update_pipe_params_after_odm_slice_count_change( 


	if (pool->funcs->build_pipe_pix_clk_params)

		pool->funcs->build_pipe_pix_clk_params(otg_master);



	if (otg_master->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE)

		resource_build_test_pattern_params(&context->res_ctx, otg_master);

	return result;

}
@@ -5082,6 +5088,7 @@ void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuratio 
{

	dml2_options->callbacks.dc = dc;

	dml2_options->callbacks.build_scaling_params = &resource_build_scaling_params;

	dml2_options->callbacks.build_test_pattern_params = &resource_build_test_pattern_params;

	dml2_options->callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;

	dml2_options->callbacks.update_pipes_for_stream_with_slice_count = &resource_update_pipes_for_stream_with_slice_count;

	dml2_options->callbacks.update_pipes_for_plane_with_slice_count = &resource_update_pipes_for_plane_with_slice_count;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+8 −0
Original line number Diff line number Diff line
@@ -2115,6 +2115,14 @@ static bool dcn32_apply_merge_split_flags_helper( 
					return false;

			}

		}



		for (i = 0; i < context->stream_count; i++) {

			struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&context->res_ctx,

					context->streams[i]);



			if (otg_master && otg_master->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE)

				resource_build_test_pattern_params(&context->res_ctx, otg_master);

		}

	}

	return true;

}

drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

+6 −0
Original line number Diff line number Diff line
@@ -1078,6 +1078,12 @@ bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const s 
				ASSERT(false);

			}

		}



		if (ctx->config.callbacks.build_test_pattern_params &&

				pipe->stream &&

				pipe->prev_odm_pipe == NULL &&

				pipe->top_pipe == NULL)

			ctx->config.callbacks.build_test_pattern_params(&state->res_ctx, pipe);

	}



	return true;

drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ struct dml2_dcn_clocks { 
struct dml2_dc_callbacks {

	struct dc *dc;

	bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);

	void (*build_test_pattern_params)(struct resource_context *res_ctx, struct pipe_ctx *otg_master);

	bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context);

	bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);

	bool (*update_pipes_for_stream_with_slice_count)(