Commit cca95436 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-fixes-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy fixes from Vinod Koul:

 - Big pile of Qualcomm DP/eDP config fixes and kaanapali PHY PLL
   lock failure fix

 - Apple typec switch/mux leak fix

 - Marvell incoorect register fix for mvebu utmi phy

 - Tegra per-pad calibration fix

* tag 'phy-fixes-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: qcom: qmp-usbc: Fix out-of-bounds array access in dp swing config
  phy: apple: atc: Fix typec switch/mux leak on unbind
  phy: spacemit: Remove incorrect clk_disable() in spacemit_usb2phy_init()
  phy: eswin: Fix incorrect error check in probe()
  phy: qcom-qmp-ufs: Fix kaanapali PHY PLL lock failure after SM8650 G4 fix
  phy: exynos5-usbdrd: fix USB 2.0 HS PHY tuning values for Exynos7870
  phy: tegra: xusb: Fix per-pad high-speed termination calibration
  phy: marvell: mvebu-a3700-utmi: fix incorrect USB2_PHY_CTRL register access
  phy: qcom: edp: Add PHY-specific LDO config for eDP low vdiff
  phy: qcom: edp: Fix AUX_CFG8 programming for DP mode
  phy: qcom: edp: Add SC7280/SC8180X swing/pre-emphasis tables
  phy: qcom: edp: Add eDP/DP mode switch support
  phy: qcom: edp: Unify generic DP/eDP swing and pre-emphasis tables
parents e216d85e ea17fc4d

drivers/phy/apple/atc.c

+22 −5
Original line number Diff line number Diff line
@@ -628,9 +628,6 @@ struct apple_atcphy { 


	struct reset_controller_dev rcdev;



	struct typec_switch *sw;

	struct typec_mux *mux;



	struct mutex lock;

};
@@ -2066,15 +2063,25 @@ static int atcphy_sw_set(struct typec_switch_dev *sw, enum typec_orientation ori 
	return 0;

}



static void atcphy_typec_switch_unregister(void *data)

{

	typec_switch_unregister(data);

}



static int atcphy_probe_switch(struct apple_atcphy *atcphy)

{

	struct typec_switch_dev *sw;

	struct typec_switch_desc sw_desc = {

		.drvdata = atcphy,

		.fwnode = atcphy->dev->fwnode,

		.set = atcphy_sw_set,

	};



	return PTR_ERR_OR_ZERO(typec_switch_register(atcphy->dev, &sw_desc));

	sw = typec_switch_register(atcphy->dev, &sw_desc);

	if (IS_ERR(sw))

		return PTR_ERR(sw);



	return devm_add_action_or_reset(atcphy->dev, atcphy_typec_switch_unregister, sw);

}



static int atcphy_mux_set(struct typec_mux_dev *mux, struct typec_mux_state *state)
@@ -2146,15 +2153,25 @@ static int atcphy_mux_set(struct typec_mux_dev *mux, struct typec_mux_state *sta 
	return atcphy_configure(atcphy, target_mode);

}



static void atcphy_typec_mux_unregister(void *data)

{

	typec_mux_unregister(data);

}



static int atcphy_probe_mux(struct apple_atcphy *atcphy)

{

	struct typec_mux_dev *mux;

	struct typec_mux_desc mux_desc = {

		.drvdata = atcphy,

		.fwnode = atcphy->dev->fwnode,

		.set = atcphy_mux_set,

	};



	return PTR_ERR_OR_ZERO(typec_mux_register(atcphy->dev, &mux_desc));

	mux = typec_mux_register(atcphy->dev, &mux_desc);

	if (IS_ERR(mux))

		return PTR_ERR(mux);



	return devm_add_action_or_reset(atcphy->dev, atcphy_typec_mux_unregister, mux);

}



static int atcphy_load_tunables(struct apple_atcphy *atcphy)

drivers/phy/eswin/phy-eic7700-sata.c

+2 −2
Original line number Diff line number Diff line
@@ -216,8 +216,8 @@ static int eic7700_sata_phy_probe(struct platform_device *pdev) 
		return -ENOENT;



	regs = devm_ioremap(dev, res->start, resource_size(res));

	if (IS_ERR(regs))

		return PTR_ERR(regs);

	if (!regs)

		return -ENOMEM;



	sata_phy->regmap = devm_regmap_init_mmio

			   (dev, regs, &eic7700_sata_phy_regmap_config);

drivers/phy/marvell/phy-mvebu-a3700-utmi.c

+2 −3
Original line number Diff line number Diff line
@@ -168,9 +168,8 @@ static int mvebu_a3700_utmi_phy_power_off(struct phy *phy) 
	u32 reg;



	/* Disable PHY pull-up and enable USB2 suspend */

	reg = readl(utmi->regs + USB2_PHY_CTRL(usb32));

	reg &= ~(RB_USB2PHY_PU | RB_USB2PHY_SUSPM(usb32));

	writel(reg, utmi->regs + USB2_PHY_CTRL(usb32));

	regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32),

			   RB_USB2PHY_PU | RB_USB2PHY_SUSPM(usb32), 0);



	/* Power down OTG module */

	if (usb32) {

drivers/phy/qualcomm/phy-qcom-edp.c

+181 −43
Original line number Diff line number Diff line
@@ -81,13 +81,15 @@ struct phy_ver_ops { 
	int (*com_clk_fwd_cfg)(const struct qcom_edp *edp);

	int (*com_configure_pll)(const struct qcom_edp *edp);

	int (*com_configure_ssc)(const struct qcom_edp *edp);

	int (*com_ldo_config)(const struct qcom_edp *edp);

};



struct qcom_edp_phy_cfg {

	bool is_edp;

	const u8 *aux_cfg;

	const u8 *vco_div_cfg;

	const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg;

	const struct qcom_edp_swing_pre_emph_cfg *dp_swing_pre_emph_cfg;

	const struct qcom_edp_swing_pre_emph_cfg *edp_swing_pre_emph_cfg;

	const struct phy_ver_ops *ver_ops;

};
@@ -116,17 +118,17 @@ struct qcom_edp { 
};



static const u8 dp_swing_hbr_rbr[4][4] = {

	{ 0x08, 0x0f, 0x16, 0x1f },

	{ 0x07, 0x0f, 0x16, 0x1f },

	{ 0x11, 0x1e, 0x1f, 0xff },

	{ 0x16, 0x1f, 0xff, 0xff },

	{ 0x1f, 0xff, 0xff, 0xff }

};



static const u8 dp_pre_emp_hbr_rbr[4][4] = {

	{ 0x00, 0x0d, 0x14, 0x1a },

	{ 0x00, 0x0e, 0x15, 0x1a },

	{ 0x00, 0x0e, 0x15, 0xff },

	{ 0x00, 0x0e, 0xff, 0xff },

	{ 0x03, 0xff, 0xff, 0xff }

	{ 0x04, 0xff, 0xff, 0xff }

};



static const u8 dp_swing_hbr2_hbr3[4][4] = {
@@ -150,6 +152,47 @@ static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg = { 
	.pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3,

};



static const u8 dp_pre_emp_hbr_rbr_v8[4][4] = {

	{ 0x00, 0x0e, 0x15, 0x1a },

	{ 0x00, 0x0e, 0x15, 0xff },

	{ 0x00, 0x0e, 0xff, 0xff },

	{ 0x00, 0xff, 0xff, 0xff }

};



static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg_v8 = {

	.swing_hbr_rbr = &dp_swing_hbr_rbr,

	.swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3,

	.pre_emphasis_hbr_rbr = &dp_pre_emp_hbr_rbr_v8,

	.pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3,

};



static const u8 dp_swing_hbr2_hbr3_v2[4][4] = {

	{ 0x27, 0x2f, 0x36, 0xff },

	{ 0x31, 0x3e, 0x3f, 0xff },

	{ 0x3a, 0x3f, 0xff, 0xff },

	{ 0xff, 0xff, 0xff, 0xff }

};



static const u8 dp_pre_emp_hbr2_hbr3_v2[4][4] = {

	{ 0x20, 0x2e, 0x35, 0xff },

	{ 0x20, 0x2e, 0x35, 0xff },

	{ 0x20, 0x2e, 0xff, 0xff },

	{ 0xff, 0xff, 0xff, 0xff }

};



static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg_v2 = {

	/*

	 * NOTE: The HPG does not specify a separate swing_hbr_rbr table.

	 * Reuse the HBR2/HBR3 table for now.

	 *

	 * TODO: Update this once the HPG explicitly defines RBR/HBR swing values.

	 */

	.swing_hbr_rbr = &dp_swing_hbr2_hbr3_v2,

	.swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3_v2,

	.pre_emphasis_hbr_rbr = &dp_pre_emp_hbr2_hbr3_v2,

	.pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3_v2,

};



static const u8 edp_swing_hbr_rbr[4][4] = {

	{ 0x07, 0x0f, 0x16, 0x1f },

	{ 0x0d, 0x16, 0x1e, 0xff },
@@ -158,7 +201,7 @@ static const u8 edp_swing_hbr_rbr[4][4] = { 
};



static const u8 edp_pre_emp_hbr_rbr[4][4] = {

	{ 0x05, 0x12, 0x17, 0x1d },

	{ 0x05, 0x11, 0x17, 0x1d },

	{ 0x05, 0x11, 0x18, 0xff },

	{ 0x06, 0x11, 0xff, 0xff },

	{ 0x00, 0xff, 0xff, 0xff }
@@ -172,10 +215,10 @@ static const u8 edp_swing_hbr2_hbr3[4][4] = { 
};



static const u8 edp_pre_emp_hbr2_hbr3[4][4] = {

	{ 0x08, 0x11, 0x17, 0x1b },

	{ 0x00, 0x0c, 0x13, 0xff },

	{ 0x05, 0x10, 0xff, 0xff },

	{ 0x00, 0xff, 0xff, 0xff }

	{ 0x0c, 0x15, 0x19, 0x1e },

	{ 0x0b, 0x15, 0x19, 0xff },

	{ 0x0e, 0x14, 0xff, 0xff },

	{ 0x0d, 0xff, 0xff, 0xff }

};



static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg = {
@@ -193,25 +236,46 @@ static const u8 edp_phy_vco_div_cfg_v4[4] = { 
	0x01, 0x01, 0x02, 0x00,

};



static const u8 edp_pre_emp_hbr_rbr_v5[4][4] = {

	{ 0x05, 0x11, 0x17, 0x1d },

static const u8 edp_pre_emp_hbr_rbr_v2[4][4] = {

	{ 0x05, 0x12, 0x17, 0x1d },

	{ 0x05, 0x11, 0x18, 0xff },

	{ 0x06, 0x11, 0xff, 0xff },

	{ 0x00, 0xff, 0xff, 0xff }

};



static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] = {

static const u8 edp_pre_emp_hbr2_hbr3_v2[4][4] = {

	{ 0x0c, 0x15, 0x19, 0x1e },

	{ 0x0b, 0x15, 0x19, 0xff },

	{ 0x08, 0x15, 0x19, 0xff },

	{ 0x0e, 0x14, 0xff, 0xff },

	{ 0x0d, 0xff, 0xff, 0xff }

};



static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg_v5 = {

static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg_v2 = {

	.swing_hbr_rbr = &edp_swing_hbr_rbr,

	.swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3,

	.pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr_v5,

	.pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v5,

	.pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr_v2,

	.pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v2,

};



static const u8 edp_swing_hbr2_hbr3_v3[4][4] = {

	{ 0x06, 0x11, 0x16, 0x1b },

	{ 0x0b, 0x19, 0x1f, 0xff },

	{ 0x18, 0x1f, 0xff, 0xff },

	{ 0x1f, 0xff, 0xff, 0xff }

};



static const u8 edp_pre_emp_hbr2_hbr3_v3[4][4] = {

	{ 0x0c, 0x15, 0x19, 0x1e },

	{ 0x09, 0x14, 0x19, 0xff },

	{ 0x0f, 0x14, 0xff, 0xff },

	{ 0x0d, 0xff, 0xff, 0xff }

};



static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg_v3 = {

	.swing_hbr_rbr = &edp_swing_hbr_rbr,

	.swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3_v3,

	.pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr,

	.pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v3,

};



static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] = {
@@ -262,12 +326,7 @@ static int qcom_edp_phy_init(struct phy *phy) 
	       DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,

	       edp->edp + DP_PHY_PD_CTL);



	/*

	 * TODO: Re-work the conditions around setting the cfg8 value

	 * when more information becomes available about why this is

	 * even needed.

	 */

	if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp)

	if (!edp->is_edp)

		aux_cfg[8] = 0xb7;



	writel(0xfc, edp->edp + DP_PHY_MODE);
@@ -291,19 +350,18 @@ static int qcom_edp_phy_init(struct phy *phy) 


static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configure_opts_dp *dp_opts)

{

	const struct qcom_edp_swing_pre_emph_cfg *cfg = edp->cfg->swing_pre_emph_cfg;

	const struct qcom_edp_swing_pre_emph_cfg *cfg;

	unsigned int v_level = 0;

	unsigned int p_level = 0;

	u8 ldo_config;

	int ret;

	u8 swing;

	u8 emph;

	int i;



	if (!cfg)

		return 0;



	if (edp->is_edp)

		cfg = &edp_phy_swing_pre_emph_cfg;

		cfg = edp->cfg->edp_swing_pre_emph_cfg;

	else

		cfg = edp->cfg->dp_swing_pre_emph_cfg;



	for (i = 0; i < dp_opts->lanes; i++) {

		v_level = max(v_level, dp_opts->voltage[i]);
@@ -321,13 +379,13 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur 
	if (swing == 0xff || emph == 0xff)

		return -EINVAL;



	ldo_config = edp->is_edp ? 0x0 : 0x1;

	ret = edp->cfg->ver_ops->com_ldo_config(edp);

	if (ret)

		return ret;



	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);

	writel(swing, edp->tx0 + TXn_TX_DRV_LVL);

	writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL);



	writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);

	writel(swing, edp->tx1 + TXn_TX_DRV_LVL);

	writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL);
@@ -551,6 +609,52 @@ static int qcom_edp_com_configure_pll_v4(const struct qcom_edp *edp) 
	return 0;

}



static int qcom_edp_ldo_config_v3(const struct qcom_edp *edp)

{

	const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;

	u32 ldo_config;



	if (!edp->is_edp)

		ldo_config = 0x0;

	else if (dp_opts->link_rate <= 2700)

		ldo_config = 0x81;

	else

		ldo_config = 0x41;



	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);

	writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG);



	return 0;

}



static int qcom_edp_ldo_config_v4(const struct qcom_edp *edp)

{

	const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;

	u32 ldo_config;



	if (!edp->is_edp)

		ldo_config = 0x0;

	else if (dp_opts->link_rate <= 2700)

		ldo_config = 0xc1;

	else

		ldo_config = 0x81;



	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);

	writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG);



	return 0;

}



static const struct phy_ver_ops qcom_edp_phy_ops_v3 = {

	.com_power_on		= qcom_edp_phy_power_on_v4,

	.com_resetsm_cntrl	= qcom_edp_phy_com_resetsm_cntrl_v4,

	.com_bias_en_clkbuflr	= qcom_edp_com_bias_en_clkbuflr_v4,

	.com_clk_fwd_cfg	= qcom_edp_com_clk_fwd_cfg_v4,

	.com_configure_pll	= qcom_edp_com_configure_pll_v4,

	.com_configure_ssc	= qcom_edp_com_configure_ssc_v4,

	.com_ldo_config		= qcom_edp_ldo_config_v3,

};



static const struct phy_ver_ops qcom_edp_phy_ops_v4 = {

	.com_power_on		= qcom_edp_phy_power_on_v4,

	.com_resetsm_cntrl	= qcom_edp_phy_com_resetsm_cntrl_v4,
@@ -558,26 +662,39 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = { 
	.com_clk_fwd_cfg	= qcom_edp_com_clk_fwd_cfg_v4,

	.com_configure_pll	= qcom_edp_com_configure_pll_v4,

	.com_configure_ssc	= qcom_edp_com_configure_ssc_v4,

	.com_ldo_config		= qcom_edp_ldo_config_v4,

};



static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = {

	.is_edp = false,

	.aux_cfg = edp_phy_aux_cfg_v5,

	.vco_div_cfg = edp_phy_vco_div_cfg_v4,

	.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5,

	.dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,

	.edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,

	.ver_ops = &qcom_edp_phy_ops_v4,

};



static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = {

	.aux_cfg = edp_phy_aux_cfg_v4,

	.vco_div_cfg = edp_phy_vco_div_cfg_v4,

	.ver_ops = &qcom_edp_phy_ops_v4,

	.dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,

	.edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v3,

	.ver_ops = &qcom_edp_phy_ops_v3,

};



static const struct qcom_edp_phy_cfg sc8180x_dp_phy_cfg = {

	.aux_cfg = edp_phy_aux_cfg_v4,

	.vco_div_cfg = edp_phy_vco_div_cfg_v4,

	.dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg_v2,

	.edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v2,

	.ver_ops = &qcom_edp_phy_ops_v3,

};



static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = {

	.aux_cfg = edp_phy_aux_cfg_v4,

	.vco_div_cfg = edp_phy_vco_div_cfg_v4,

	.swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,

	.dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,

	.edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,

	.ver_ops = &qcom_edp_phy_ops_v4,

};
@@ -585,7 +702,8 @@ static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = { 
	.is_edp = true,

	.aux_cfg = edp_phy_aux_cfg_v4,

	.vco_div_cfg = edp_phy_vco_div_cfg_v4,

	.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,

	.dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,

	.edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,

	.ver_ops = &qcom_edp_phy_ops_v4,

};
@@ -754,6 +872,24 @@ static int qcom_edp_com_configure_pll_v6(const struct qcom_edp *edp) 
	return 0;

}



static int qcom_edp_ldo_config_v6(const struct qcom_edp *edp)

{

	const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;

	u32 ldo_config;



	if (!edp->is_edp)

		ldo_config = 0x0;

	else if (dp_opts->link_rate <= 2700)

		ldo_config = 0x51;

	else

		ldo_config = 0x91;



	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);

	writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG);



	return 0;

}



static const struct phy_ver_ops qcom_edp_phy_ops_v6 = {

	.com_power_on		= qcom_edp_phy_power_on_v6,

	.com_resetsm_cntrl	= qcom_edp_phy_com_resetsm_cntrl_v6,
@@ -761,12 +897,14 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = { 
	.com_clk_fwd_cfg	= qcom_edp_com_clk_fwd_cfg_v4,

	.com_configure_pll	= qcom_edp_com_configure_pll_v6,

	.com_configure_ssc	= qcom_edp_com_configure_ssc_v6,

	.com_ldo_config		= qcom_edp_ldo_config_v6,

};



static struct qcom_edp_phy_cfg x1e80100_phy_cfg = {

	.aux_cfg = edp_phy_aux_cfg_v4,

	.vco_div_cfg = edp_phy_vco_div_cfg_v4,

	.swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,

	.dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,

	.edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,

	.ver_ops = &qcom_edp_phy_ops_v6,

};
@@ -940,12 +1078,14 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 = { 
	.com_clk_fwd_cfg	= qcom_edp_com_clk_fwd_cfg_v8,

	.com_configure_pll	= qcom_edp_com_configure_pll_v8,

	.com_configure_ssc	= qcom_edp_com_configure_ssc_v8,

	.com_ldo_config		= qcom_edp_ldo_config_v6,

};



static struct qcom_edp_phy_cfg glymur_phy_cfg = {

	.aux_cfg = edp_phy_aux_cfg_v8,

	.vco_div_cfg = edp_phy_vco_div_cfg_v8,

	.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5,

	.dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg_v8,

	.edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,

	.ver_ops = &qcom_edp_phy_ops_v8,

};
@@ -954,7 +1094,6 @@ static int qcom_edp_phy_power_on(struct phy *phy) 
	const struct qcom_edp *edp = phy_get_drvdata(phy);

	u32 bias0_en, drvr0_en, bias1_en, drvr1_en;

	unsigned long pixel_freq;

	u8 ldo_config = 0x0;

	int ret;

	u32 val;

	u8 cfg1;
@@ -963,11 +1102,10 @@ static int qcom_edp_phy_power_on(struct phy *phy) 
	if (ret)

		return ret;



	if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp)

		ldo_config = 0x1;

	ret = edp->cfg->ver_ops->com_ldo_config(edp);

	if (ret)

		return ret;



	writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);

	writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);

	writel(0x00, edp->tx0 + TXn_LANE_MODE_1);

	writel(0x00, edp->tx1 + TXn_LANE_MODE_1);
@@ -1347,7 +1485,7 @@ static const struct of_device_id qcom_edp_phy_match_table[] = { 
	{ .compatible = "qcom,glymur-dp-phy", .data = &glymur_phy_cfg, },

	{ .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, },

	{ .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, },

	{ .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, },

	{ .compatible = "qcom,sc8180x-edp-phy", .data = &sc8180x_dp_phy_cfg, },

	{ .compatible = "qcom,sc8280xp-dp-phy", .data = &sc8280xp_dp_phy_cfg, },

	{ .compatible = "qcom,sc8280xp-edp-phy", .data = &sc8280xp_edp_phy_cfg, },

	{ .compatible = "qcom,x1e80100-dp-phy", .data = &x1e80100_phy_cfg, },

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+1 −0
Original line number Diff line number Diff line
@@ -1112,6 +1112,7 @@ static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = { 
	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e),