Commit ccaeeec5 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/lpa2-prep' into for-next/core 

* for-next/lpa2-prep:
  arm64: mm: get rid of kimage_vaddr global variable
  arm64: mm: Take potential load offset into account when KASLR is off
  arm64: kernel: Disable latent_entropy GCC plugin in early C runtime
  arm64: Add ARM64_HAS_LPA2 CPU capability
  arm64/mm: Add FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2]
  arm64/mm: Update tlb invalidation routines for FEAT_LPA2
  arm64/mm: Add lpa2_is_enabled() kvm_lpa2_is_enabled() stubs
  arm64/mm: Modify range-based tlbi to decrement scale
parents 88619527 376f5a3b

arch/arm64/include/asm/cpufeature.h

+5 −0
Original line number Diff line number Diff line
@@ -820,6 +820,11 @@ static inline bool system_supports_tlb_range(void) 
	return alternative_has_cap_unlikely(ARM64_HAS_TLB_RANGE);

}



static inline bool system_supports_lpa2(void)

{

	return cpus_have_final_cap(ARM64_HAS_LPA2);

}



int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);

bool try_emulate_mrs(struct pt_regs *regs, u32 isn);

arch/arm64/include/asm/kernel-pgtable.h

+6 −21
Original line number Diff line number Diff line
@@ -37,27 +37,12 @@ 




/*

 * If KASLR is enabled, then an offset K is added to the kernel address

 * space. The bottom 21 bits of this offset are zero to guarantee 2MB

 * alignment for PA and VA.

 *

 * For each pagetable level of the swapper, we know that the shift will

 * be larger than 21 (for the 4KB granule case we use section maps thus

 * the smallest shift is actually 30) thus there is the possibility that

 * KASLR can increase the number of pagetable entries by 1, so we make

 * room for this extra entry.

 *

 * Note KASLR cannot increase the number of required entries for a level

 * by more than one because it increments both the virtual start and end

 * addresses equally (the extra entry comes from the case where the end

 * address is just pushed over a boundary and the start address isn't).

 * A relocatable kernel may execute from an address that differs from the one at

 * which it was linked. In the worst case, its runtime placement may intersect

 * with two adjacent PGDIR entries, which means that an additional page table

 * may be needed at each subordinate level.

 */



#ifdef CONFIG_RANDOMIZE_BASE

#define EARLY_KASLR	(1)

#else

#define EARLY_KASLR	(0)

#endif

#define EXTRA_PAGE	__is_defined(CONFIG_RELOCATABLE)



#define SPAN_NR_ENTRIES(vstart, vend, shift) \

	((((vend) - 1) >> (shift)) - ((vstart) >> (shift)) + 1)
@@ -83,7 +68,7 @@ 
			+ EARLY_PGDS((vstart), (vend), add) 	/* each PGDIR needs a next level page table */	\

			+ EARLY_PUDS((vstart), (vend), add)	/* each PUD needs a next level page table */	\

			+ EARLY_PMDS((vstart), (vend), add))	/* each PMD needs a next level page table */

#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR, _end, EARLY_KASLR))

#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR, _end, EXTRA_PAGE))



/* the initial ID map may need two extra pages if it needs to be extended */

#if VA_BITS < 48

arch/arm64/include/asm/kvm_pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -25,6 +25,8 @@ 
#define KVM_PGTABLE_MIN_BLOCK_LEVEL	2U

#endif



#define kvm_lpa2_is_enabled()		false



static inline u64 kvm_get_parange(u64 mmfr0)

{

	u64 parange = cpuid_feature_extract_unsigned_field(mmfr0,

arch/arm64/include/asm/memory.h

+2 −4
Original line number Diff line number Diff line
@@ -182,6 +182,7 @@ 
#include <linux/types.h>

#include <asm/boot.h>

#include <asm/bug.h>

#include <asm/sections.h>



#if VA_BITS > 48

extern u64			vabits_actual;
@@ -193,15 +194,12 @@ extern s64 memstart_addr; 
/* PHYS_OFFSET - the physical address of the start of memory. */

#define PHYS_OFFSET		({ VM_BUG_ON(memstart_addr & 1); memstart_addr; })



/* the virtual base of the kernel image */

extern u64			kimage_vaddr;



/* the offset between the kernel virtual and physical mappings */

extern u64			kimage_voffset;



static inline unsigned long kaslr_offset(void)

{

	return kimage_vaddr - KIMAGE_VADDR;

	return (u64)&_text - KIMAGE_VADDR;

}



#ifdef CONFIG_RANDOMIZE_BASE

arch/arm64/include/asm/pgtable-prot.h

+2 −0
Original line number Diff line number Diff line
@@ -71,6 +71,8 @@ extern bool arm64_use_ng_mappings; 
#define PTE_MAYBE_NG		(arm64_use_ng_mappings ? PTE_NG : 0)

#define PMD_MAYBE_NG		(arm64_use_ng_mappings ? PMD_SECT_NG : 0)



#define lpa2_is_enabled()	false



/*

 * If we have userspace only BTI we don't want to mark kernel pages

 * guarded even if the system does support BTI.