Commit ccd73c57 authored by Oliver Upton's avatar Oliver Upton
Browse files

Merge tag 'irqchip-gic-v5-host' into kvmarm/next 



GICv5 initial host support

Add host kernel support for the new arm64 GICv5 architecture, which is
quite a departure from the previous ones.

Include support for the full gamut of the architecture (interrupt
routing and delivery to CPUs, wired interrupts, MSIs, and interrupt
translation).

* tag 'irqchip-gic-v5-host': (32 commits)
  arm64: smp: Fix pNMI setup after GICv5 rework
  arm64: Kconfig: Enable GICv5
  docs: arm64: gic-v5: Document booting requirements for GICv5
  irqchip/gic-v5: Add GICv5 IWB support
  irqchip/gic-v5: Add GICv5 ITS support
  irqchip/msi-lib: Add IRQ_DOMAIN_FLAG_FWNODE_PARENT handling
  irqchip/gic-v3: Rename GICv3 ITS MSI parent
  PCI/MSI: Add pci_msi_map_rid_ctlr_node() helper function
  of/irq: Add of_msi_xlate() helper function
  irqchip/gic-v5: Enable GICv5 SMP booting
  irqchip/gic-v5: Add GICv5 LPI/IPI support
  irqchip/gic-v5: Add GICv5 IRS/SPI support
  irqchip/gic-v5: Add GICv5 PPI support
  arm64: Add support for GICv5 GSB barriers
  arm64: smp: Support non-SGIs for IPIs
  arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability
  arm64: cpucaps: Rename GICv3 CPU interface capability
  arm64: Disable GICv5 read/write/instruction traps
  arm64/sysreg: Add ICH_HFGITR_EL2
  arm64/sysreg: Add ICH_HFGWTR_EL2
  ...

Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parents 3318e42b 65a5520a

Documentation/arch/arm64/booting.rst

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@@ -223,6 +223,47 @@ Before jumping into the kernel, the following conditions must be met: 


    - SCR_EL3.HCE (bit 8) must be initialised to 0b1.



  For systems with a GICv5 interrupt controller to be used in v5 mode:



  - If the kernel is entered at EL1 and EL2 is present:



      - ICH_HFGRTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_PPI_HMRn_EL1 (bit 16) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_IAFFIDR_EL1 (bit 7) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_HPPIR_EL1 (bit 4) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_HAPR_EL1 (bit 3) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_IDRn_EL1 (bit 1) must be initialised to 0b1.

      - ICH_HFGRTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1.



      - ICH_HFGWTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1.

      - ICH_HFGWTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1.



      - ICH_HFGITR_EL2.GICRCDNMIA (bit 10) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICRCDIA (bit 9) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDDI (bit 8) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDEOI (bit 7) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDHM (bit 6) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDRCFG (bit 5) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDPEND (bit 4) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDAFF (bit 3) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDPRI (bit 2) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDDIS (bit 1) must be initialised to 0b1.

      - ICH_HFGITR_EL2.GICCDEN (bit 0) must be initialised to 0b1.



  - The DT or ACPI tables must describe a GICv5 interrupt controller.



  For systems with a GICv3 interrupt controller to be used in v3 mode:

  - If EL3 is present:

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (IWB)



maintainers:

  - Lorenzo Pieralisi <lpieralisi@kernel.org>

  - Marc Zyngier <maz@kernel.org>



description: |

  The GICv5 architecture defines the guidelines to implement GICv5

  compliant interrupt controllers for AArch64 systems.



  The GICv5 specification can be found at

  https://developer.arm.com/documentation/aes0070



  GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible

  for translating wire signals into interrupt messages to the GICv5 ITS.



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  compatible:

    const: arm,gic-v5-iwb



  reg:

    items:

      - description: IWB control frame



  "#address-cells":

    const: 0



  "#interrupt-cells":

    description: |

      The 1st cell corresponds to the IWB wire.



      The 2nd cell is the flags, encoded as follows:

      bits[3:0] trigger type and level flags.



      1 = low-to-high edge triggered

      2 = high-to-low edge triggered

      4 = active high level-sensitive

      8 = active low level-sensitive



    const: 2



  interrupt-controller: true



  msi-parent:

    maxItems: 1



required:

  - compatible

  - reg

  - "#interrupt-cells"

  - interrupt-controller

  - msi-parent



additionalProperties: false



examples:

  - |

    interrupt-controller@2f000000 {

      compatible = "arm,gic-v5-iwb";

      reg = <0x2f000000 0x10000>;



      #address-cells = <0>;



      #interrupt-cells = <2>;

      interrupt-controller;



      msi-parent = <&its0 64>;

    };

...

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM Generic Interrupt Controller, version 5



maintainers:

  - Lorenzo Pieralisi <lpieralisi@kernel.org>

  - Marc Zyngier <maz@kernel.org>



description: |

  The GICv5 architecture defines the guidelines to implement GICv5

  compliant interrupt controllers for AArch64 systems.



  The GICv5 specification can be found at

  https://developer.arm.com/documentation/aes0070



  The GICv5 architecture is composed of multiple components:

    - one or more IRS (Interrupt Routing Service)

    - zero or more ITS (Interrupt Translation Service)



  The architecture defines:

    - PE-Private Peripheral Interrupts (PPI)

    - Shared Peripheral Interrupts (SPI)

    - Logical Peripheral Interrupts (LPI)



allOf:

  - $ref: /schemas/interrupt-controller.yaml#



properties:

  compatible:

    const: arm,gic-v5



  "#address-cells":

    enum: [ 1, 2 ]



  "#size-cells":

    enum: [ 1, 2 ]



  ranges: true



  "#interrupt-cells":

    description: |

      The 1st cell corresponds to the INTID.Type field in the INTID; 1 for PPI,

      3 for SPI. LPI interrupts must not be described in the bindings since

      they are allocated dynamically by the software component managing them.



      The 2nd cell contains the interrupt INTID.ID field.



      The 3rd cell is the flags, encoded as follows:

      bits[3:0] trigger type and level flags.



        1 = low-to-high edge triggered

        2 = high-to-low edge triggered

        4 = active high level-sensitive

        8 = active low level-sensitive



    const: 3



  interrupt-controller: true



  interrupts:

    description:

      The VGIC maintenance interrupt.

    maxItems: 1



required:

  - compatible

  - "#address-cells"

  - "#size-cells"

  - ranges

  - "#interrupt-cells"

  - interrupt-controller



patternProperties:

  "^irs@[0-9a-f]+$":

    type: object

    description:

      GICv5 has one or more Interrupt Routing Services (IRS) that are

      responsible for handling IRQ state and routing.



    additionalProperties: false



    properties:

      compatible:

        const: arm,gic-v5-irs



      reg:

        minItems: 1

        items:

          - description: IRS config frames

          - description: IRS setlpi frames



      reg-names:

        description:

          Describe config and setlpi frames that are present.

          "ns-" stands for non-secure, "s-" for secure, "realm-" for realm

          and "el3-" for EL3.

        minItems: 1

        maxItems: 8

        items:

          enum: [ ns-config, s-config, realm-config, el3-config, ns-setlpi,

                  s-setlpi, realm-setlpi, el3-setlpi ]



      "#address-cells":

        enum: [ 1, 2 ]



      "#size-cells":

        enum: [ 1, 2 ]



      ranges: true



      dma-noncoherent:

        description:

          Present if the GIC IRS permits programming shareability and

          cacheability attributes but is connected to a non-coherent

          downstream interconnect.



      cpus:

        description:

          CPUs managed by the IRS.



      arm,iaffids:

        $ref: /schemas/types.yaml#/definitions/uint16-array

        description:

          Interrupt AFFinity ID (IAFFID) associated with the CPU whose

          CPU node phandle is at the same index in the cpus array.



    patternProperties:

      "^its@[0-9a-f]+$":

        type: object

        description:

          GICv5 has zero or more Interrupt Translation Services (ITS) that are

          used to route Message Signalled Interrupts (MSI) to the CPUs. Each

          ITS is connected to an IRS.

        additionalProperties: false



        properties:

          compatible:

            const: arm,gic-v5-its



          reg:

            items:

              - description: ITS config frames



          reg-names:

            description:

              Describe config frames that are present.

              "ns-" stands for non-secure, "s-" for secure, "realm-" for realm

              and "el3-" for EL3.

            minItems: 1

            maxItems: 4

            items:

              enum: [ ns-config, s-config, realm-config, el3-config ]



          "#address-cells":

            enum: [ 1, 2 ]



          "#size-cells":

            enum: [ 1, 2 ]



          ranges: true



          dma-noncoherent:

            description:

              Present if the GIC ITS permits programming shareability and

              cacheability attributes but is connected to a non-coherent

              downstream interconnect.



        patternProperties:

          "^msi-controller@[0-9a-f]+$":

            type: object

            description:

              GICv5 ITS has one or more translate register frames.

            additionalProperties: false



            properties:

              reg:

                items:

                  - description: ITS translate frames



              reg-names:

                description:

                  Describe translate frames that are present.

                  "ns-" stands for non-secure, "s-" for secure, "realm-" for realm

                  and "el3-" for EL3.

                minItems: 1

                maxItems: 4

                items:

                  enum: [ ns-translate, s-translate, realm-translate, el3-translate ]



              "#msi-cells":

                description:

                  The single msi-cell is the DeviceID of the device which will

                  generate the MSI.

                const: 1



              msi-controller: true



            required:

              - reg

              - reg-names

              - "#msi-cells"

              - msi-controller



        required:

          - compatible

          - reg

          - reg-names



    required:

      - compatible

      - reg

      - reg-names

      - cpus

      - arm,iaffids



additionalProperties: false



examples:

  - |

    interrupt-controller {

      compatible = "arm,gic-v5";



      #interrupt-cells = <3>;

      interrupt-controller;



      #address-cells = <1>;

      #size-cells = <1>;

      ranges;



      interrupts = <1 25 4>;



      irs@2f1a0000 {

        compatible = "arm,gic-v5-irs";

        reg = <0x2f1a0000 0x10000>;  // IRS_CONFIG_FRAME

        reg-names = "ns-config";



        #address-cells = <1>;

        #size-cells = <1>;

        ranges;



        cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;

        arm,iaffids = /bits/ 16 <0 1 2 3 4 5 6 7>;



        its@2f120000 {

          compatible = "arm,gic-v5-its";

          reg = <0x2f120000 0x10000>;   // ITS_CONFIG_FRAME

          reg-names = "ns-config";



          #address-cells = <1>;

          #size-cells = <1>;

          ranges;



          msi-controller@2f130000 {

            reg = <0x2f130000 0x10000>;   // ITS_TRANSLATE_FRAME

            reg-names = "ns-translate";



            #msi-cells = <1>;

            msi-controller;

          };

        };

      };

    };

...

MAINTAINERS

+10 −0
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@@ -1964,6 +1964,16 @@ F: drivers/irqchip/irq-gic*.[ch] 
F:	include/linux/irqchip/arm-gic*.h

F:	include/linux/irqchip/arm-vgic-info.h









ARM GENERIC INTERRUPT CONTROLLER V5 DRIVERS









M:	Lorenzo Pieralisi <lpieralisi@kernel.org>









M:	Marc Zyngier <maz@kernel.org>









L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)









S:	Maintained









F:	Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5*.yaml









F:	drivers/irqchip/irq-gic-its-msi-parent.[ch]









F:	drivers/irqchip/irq-gic-v5*.[ch]









F:	include/linux/irqchip/arm-gic-v5.h

















ARM HDLCD DRM DRIVER









M:	Liviu Dudau <liviu.dudau@arm.com>









S:	Supported
































arch/arm64/Kconfig



+1
−0






























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@@ -129,6 +129,7 @@ config ARM64







	select ARM_GIC_V2M if PCI









	select ARM_GIC_V3









	select ARM_GIC_V3_ITS if PCI









	select ARM_GIC_V5









	select ARM_PSCI_FW









	select BUILDTIME_TABLE_SORT









	select CLONE_BACKWARDS