Commit ccdb96cc authored by Vinod Govindapillai's avatar Vinod Govindapillai
Browse files

drm/i915/fbc: keep FBC disabled if selective update is on in xe2lpd 



FBC was disabled in case PSR2 selective update in display 12 to
14 as part of a wa. From xe2lpd onwards there is a logic to be
implemented to decide between FBC and selective update. Until
that logic is implemented keep FBC disabled in case selective
update is enabled.

v1: updated patch description and some explanation and todo

Signed-off-by: default avatarVinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: default avatarJouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250321094529.197397-2-vinod.govindapillai@intel.com
parent 88c1f9a4

drivers/gpu/drm/i915/display/intel_fbc.c

+8 −6
Original line number Diff line number Diff line
@@ -1465,13 +1465,15 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, 
	 * Recommendation is to keep this combination disabled

	 * Bspec: 50422 HSD: 14010260002

	 *

	 * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot

	 * coexist. So if PSR2 selective fetch is supported then mark that

	 * FBC is not supported.

	 * TODO: Need a logic to decide between PSR2 and FBC Dirty rect

	 * TODO: Implement a logic to select between PSR2 selective fetch and

	 * FBC based on Bspec: 68881 in xe2lpd onwards.

	 *

	 * As we still see some strange underruns in those platforms while

	 * disabling PSR2, keep FBC disabled in case of selective update is on

	 * until the selection logic is implemented.

	 */

	if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display)) &&

	    crtc_state->has_sel_update && !crtc_state->has_panel_replay) {

	if (DISPLAY_VER(display) >= 12 && crtc_state->has_sel_update &&

	    !crtc_state->has_panel_replay) {

		plane_state->no_fbc_reason = "PSR2 enabled";

		return 0;

	}