Commit ccdf745b authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type 



The variable PLL2 clock type was superseded by the more generic
variable fractional 8.25 PLL clock type, and its sole user was converted.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8e5564958002351f29435f63de1304fb3b51a725.1721648548.git.geert+renesas@glider.be
parent 2cf316b4

drivers/clk/renesas/rcar-gen4-cpg.c

+0 −9
Original line number Diff line number Diff line
@@ -440,15 +440,6 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, 
		div = cpg_pll_config->pll1_div;

		break;



	case CLK_TYPE_GEN4_PLL2_VAR:

		/*

		 * PLL2 is implemented as a custom clock, to change the

		 * multiplier when cpufreq changes between normal and boost

		 * modes.

		 */

		return cpg_pll_clk_register(core->name, __clk_get_name(parent),

					    base, 2, &cpg_pll_v8_25_clk_ops);



	case CLK_TYPE_GEN4_PLL2:

		mult = cpg_pll_config->pll2_mult;

		div = cpg_pll_config->pll2_div;

drivers/clk/renesas/rcar-gen4-cpg.h

+0 −1
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ enum rcar_gen4_clk_types { 
	CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,

	CLK_TYPE_GEN4_PLL1,

	CLK_TYPE_GEN4_PLL2,

	CLK_TYPE_GEN4_PLL2_VAR,

	CLK_TYPE_GEN4_PLL2X_3X,	/* r8a779a0 only */

	CLK_TYPE_GEN4_PLL3,

	CLK_TYPE_GEN4_PLL4,