Commit cd268e30 authored by David Virag's avatar David Virag Committed by Krzysztof Kozlowski
Browse files

dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS 



CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD,
MMC_SDIO), and USB30DRD.

Add clock indices and bindings documentation for CMU_FSYS domain.

Signed-off-by: default avatarDavid Virag <virag.david003@gmail.com>
Reviewed-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220601233743.56317-2-virag.david003@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent f2906aa8

Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml

+27 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ properties: 
    enum:

      - samsung,exynos7885-cmu-top

      - samsung,exynos7885-cmu-core

      - samsung,exynos7885-cmu-fsys

      - samsung,exynos7885-cmu-peri



  clocks:
@@ -88,6 +89,32 @@ allOf: 
            - const: dout_core_cci

            - const: dout_core_g3d



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos7885-cmu-fsys



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_FSYS bus clock (from CMU_TOP)

            - description: MMC_CARD clock (from CMU_TOP)

            - description: MMC_EMBD clock (from CMU_TOP)

            - description: MMC_SDIO clock (from CMU_TOP)

            - description: USB30DRD clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_fsys_bus

            - const: dout_fsys_mmc_card

            - const: dout_fsys_mmc_embd

            - const: dout_fsys_mmc_sdio

            - const: dout_fsys_usb30drd



  - if:

      properties:

        compatible:

include/dt-bindings/clock/exynos7885.h

+30 −1
Original line number Diff line number Diff line
@@ -54,7 +54,22 @@ 
#define CLK_GOUT_PERI_USI0		43

#define CLK_GOUT_PERI_USI1		44

#define CLK_GOUT_PERI_USI2		45

#define TOP_NR_CLK			46

#define CLK_MOUT_FSYS_BUS		46

#define CLK_MOUT_FSYS_MMC_CARD		47

#define CLK_MOUT_FSYS_MMC_EMBD		48

#define CLK_MOUT_FSYS_MMC_SDIO		49

#define CLK_MOUT_FSYS_USB30DRD		50

#define CLK_DOUT_FSYS_BUS		51

#define CLK_DOUT_FSYS_MMC_CARD		52

#define CLK_DOUT_FSYS_MMC_EMBD		53

#define CLK_DOUT_FSYS_MMC_SDIO		54

#define CLK_DOUT_FSYS_USB30DRD		55

#define CLK_GOUT_FSYS_BUS		56

#define CLK_GOUT_FSYS_MMC_CARD		57

#define CLK_GOUT_FSYS_MMC_EMBD		58

#define CLK_GOUT_FSYS_MMC_SDIO		59

#define CLK_GOUT_FSYS_USB30DRD		60

#define TOP_NR_CLK			61



/* CMU_CORE */

#define CLK_MOUT_CORE_BUS_USER		1
@@ -112,4 +127,18 @@ 
#define CLK_GOUT_WDT1_PCLK		43

#define PERI_NR_CLK			44



/* CMU_FSYS */

#define CLK_MOUT_FSYS_BUS_USER		1

#define CLK_MOUT_FSYS_MMC_CARD_USER	2

#define CLK_MOUT_FSYS_MMC_EMBD_USER	3

#define CLK_MOUT_FSYS_MMC_SDIO_USER	4

#define CLK_MOUT_FSYS_USB30DRD_USER	4

#define CLK_GOUT_MMC_CARD_ACLK		5

#define CLK_GOUT_MMC_CARD_SDCLKIN	6

#define CLK_GOUT_MMC_EMBD_ACLK		7

#define CLK_GOUT_MMC_EMBD_SDCLKIN	8

#define CLK_GOUT_MMC_SDIO_ACLK		9

#define CLK_GOUT_MMC_SDIO_SDCLKIN	10

#define FSYS_NR_CLK			11



#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */