Commit cd6df3f3 authored by H. Peter Anvin (Intel)'s avatar H. Peter Anvin (Intel) Committed by Borislav Petkov (AMD)
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x86/cpu: Add MSR numbers for FRED configuration 



Add MSR numbers for the FRED configuration registers per FRED spec 5.0.

Originally-by: default avatarMegha Dey <megha.dey@intel.com>
Signed-off-by: default avatarH. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: default avatarXin Li <xin3.li@intel.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Tested-by: default avatarShan Kang <shan.kang@intel.com>
Link: https://lore.kernel.org/r/20231205105030.8698-13-xin3.li@intel.com
parent ff45746f

arch/x86/include/asm/msr-index.h

+12 −1
Original line number Diff line number Diff line
@@ -36,8 +36,19 @@ 
#define EFER_FFXSR		(1<<_EFER_FFXSR)

#define EFER_AUTOIBRS		(1<<_EFER_AUTOIBRS)



/* Intel MSRs. Some also available on other CPUs */

/* FRED MSRs */

#define MSR_IA32_FRED_RSP0	0x1cc			/* Level 0 stack pointer */

#define MSR_IA32_FRED_RSP1	0x1cd			/* Level 1 stack pointer */

#define MSR_IA32_FRED_RSP2	0x1ce			/* Level 2 stack pointer */

#define MSR_IA32_FRED_RSP3	0x1cf			/* Level 3 stack pointer */

#define MSR_IA32_FRED_STKLVLS	0x1d0			/* Exception stack levels */

#define MSR_IA32_FRED_SSP0	MSR_IA32_PL0_SSP	/* Level 0 shadow stack pointer */

#define MSR_IA32_FRED_SSP1	0x1d1			/* Level 1 shadow stack pointer */

#define MSR_IA32_FRED_SSP2	0x1d2			/* Level 2 shadow stack pointer */

#define MSR_IA32_FRED_SSP3	0x1d3			/* Level 3 shadow stack pointer */

#define MSR_IA32_FRED_CONFIG	0x1d4			/* Entrypoint and interrupt stack level */



/* Intel MSRs. Some also available on other CPUs */

#define MSR_TEST_CTRL				0x00000033

#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT	29

#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT		BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)

tools/arch/x86/include/asm/msr-index.h

+12 −1
Original line number Diff line number Diff line
@@ -36,8 +36,19 @@ 
#define EFER_FFXSR		(1<<_EFER_FFXSR)

#define EFER_AUTOIBRS		(1<<_EFER_AUTOIBRS)



/* Intel MSRs. Some also available on other CPUs */

/* FRED MSRs */

#define MSR_IA32_FRED_RSP0	0x1cc			/* Level 0 stack pointer */

#define MSR_IA32_FRED_RSP1	0x1cd			/* Level 1 stack pointer */

#define MSR_IA32_FRED_RSP2	0x1ce			/* Level 2 stack pointer */

#define MSR_IA32_FRED_RSP3	0x1cf			/* Level 3 stack pointer */

#define MSR_IA32_FRED_STKLVLS	0x1d0			/* Exception stack levels */

#define MSR_IA32_FRED_SSP0	MSR_IA32_PL0_SSP	/* Level 0 shadow stack pointer */

#define MSR_IA32_FRED_SSP1	0x1d1			/* Level 1 shadow stack pointer */

#define MSR_IA32_FRED_SSP2	0x1d2			/* Level 2 shadow stack pointer */

#define MSR_IA32_FRED_SSP3	0x1d3			/* Level 3 shadow stack pointer */

#define MSR_IA32_FRED_CONFIG	0x1d4			/* Entrypoint and interrupt stack level */



/* Intel MSRs. Some also available on other CPUs */

#define MSR_TEST_CTRL				0x00000033

#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT	29

#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT		BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)